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The unpredictability of real-world graph workloads complicates the realization of high-performance graph analytics on the GPU. For example, variance in sparsity and neighbor commonality can dramatically alter computing costs and memory-access patterns, even within different regions of the same graph.In this paper, we investigate Jaccard similarity, a metric that measures the similarity of two sets. We compare and contrast the performance an edge-centric parallelization of Jaccard similarity with respect to the vertex-centric approach from NVIDIA’s cuGraph library. We then characterize the impact of graph metrics (e.g., average degree, maximum degree, Gini index) on the performance of edge-centric and vertex-centric kernels. By combining the above graph metrics with performance metrics (e.g., bandwidth utilization and thread activity), we deliver insight into why certain graphs benefit from edge-centric over vertex-centric parallelization, while other graphs benefit conversely. Finally, based on these results, we make a case for sparsity-aware parallelization, i.e., choosing between an edge-centric or a vertex-centric parallelized kernel, for improved performance by showing that selecting the best-performing parallelized kernel can deliver a geometric mean speedup of 3.2× over the reference cuGraph kernel on an NVIDIA A100 GPU. 

Mission-critical edge applications often demand FFTs under the stringent constraints of performance, accuracy, and power. With many vendor FFT libraries only supporting power-of-two FFTs, the need for zero-padding of non-power-of-two inputs to facilitate the use of power-of-two FFT libraries can degrade accuracy by introducing spectral artifacts and increase power consumption by unnecessarily computing on zeroes. Furthermore, striking the right balance between performance, accuracy, and power can significantly impact developer productivity and, in turn, delay deployment.To address the limitations imposed by these constraints, we realize a mixed-radix FFT (MR-FFT) for 1,600-and 8,000-point inputs on a low-power FPGA that uses a high-level synthesis approach to enable efficient design exploration. Specifically, our MR-FFT on a krtkl Snickerdoodle board, which features an ARM Cortex-A9 CPU and Xilinx Artix-7 FPGA, (1) maintains or improves accuracy when compared to power-of-two FFT with zero-padding, (2) achieves 2.5× lower power consumption and 1.3× better energy efficiency over a Raspberry Pi CM5 GPU, and (3) delivers an average of 4.9× speedup over the NumPy FFT implementation on the Cortex-A9 CPU. 

Traditionally, FPGA programming has been done via a hardware description language (HDL). An HDL provides fine-grained control over reconfigurable hardware but with limited productivity due to a steep learning curve and tedious design cycle. Thus, high-level synthesis (HLS) approaches have been a significant boon to productivity, and in recent years, OpenCL has emerged as a vendor-agnostic HLS language that offers the added benefit of interoperation with other OpenCL platforms (e.g., CPU, GPU, DSP) and existing OpenCL software. However, OpenCL's productivity can also suffer from tedious boilerplate code and the need to manually coordinate the host (i.e., CPU) and device (i.e., FPGA or other device). So, we present MetaCL, a compiler-assisted interface that takes OpenCL kernel functions as input and automatically generates OpenCL host-side code as output. MetaCL produces more efficient and readable host-side code, ensures portability, and introduces minimal additional runtime overhead compared to unassisted OpenCL development.