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With the increasing complexity and connectivity of modern digital systems, verification has emerged as a critical bottleneck in the design flow. Assertion-Based Verification (ABV) has proven to be one of the most effective techniques for presilicon verification. Once assertions are generated, they can be synthesized into hardware monitors and incorporated into the design debug infrastructure. Many Design-for-Debug (DfD) methodologies leverage such hardware monitors to enhance the observability and controllability of internal system behavior, thereby accelerating verification and reducing time to market. Post-silicon debugging also benefits from the improved observability provided by these monitors. Furthermore, hardware monitors can be employed during runtime to detect and report undesired behaviors. To enable the seamless use of assertions, which are originally expressed in verification languages, throughout the entire design life cycle, several assertion synthesis approaches have been proposed. The objective of this survey is to present the existing assertion synthesis methods reported in the literature, discuss their current limitations, and identify directions for future research and improvement. 

Functional reverse engineering of flattened Field Programmable Gate Array (FPGA) Look-Up Table (LUT) netlists to Register Transfer Level (RTL) representation is essential to understand, reconstruct and enhance the existing legacy designs. Recent advances in machine learning show promising results in solving EDA problems. In this paper, we propose a tool, RELUT-GNN that uses Graph Neural Networks (GNNs) to extract high-level functionality of data path elements from LUT-level netlists. For GNNs, the netlist structure is represented as a graph with FPGA leaf cells as nodes and the nets among them as edges. We extract features for each node and train the GNN to learn the structure of the netlist by aggregating their node features and their neighbors. The training dataset includes a comprehensive custom dataset consisting of various Operators, Shifters, Counters, FSMs, and their combinations of varying bit widths. The model is validated and tested on unseen real-world designs obtained from Opencores and ITC99. It is observed that RELUT-GNN achieved a combined accuracy of 97.12% for the classification of selected benchmarks from arithmetic and DSP cores and the ITC‘99 benchmarks. 

Verification of FPGA-based designs and comprehension of legacy designs can be aided by the process of reverse engineering the flattened Look-up Table (LUT) level netlists to high-level RTL representations. We propose a tool flow to extract Finite State Controllers by identifying control registers and progressively improving the accuracy of register classification. A control unit consists of one or more Finite State Machines (FSMs) which manage the execution of datapath units. The proposed tool flow has two phases. Phase 1 extracts the potential state/control registers. Phase 2 identifies the exact list of state/control registers and groups FSMs. The main goal of the proposed work is to improve the accuracy of control register identification. Three types of controllers used for experimental evaluation are standalone FSM designs with no datapath units, datapaths with a single FSM, and datapaths with multiple FSMs. Accuracy is observed to be 73% to 100% in controllers with multiple FSMs, 100% in controllers with a single FSM and standalone FSM controller designs. The average accuracy of control register detection over all the real-world designs considered is 98%.