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Sleep is an intrinsic part of human life, and recent advancements in wearable technology and machine learning have promised continuous and non-invasive methods of tracking sleep health and patterns, providing an important facet to a more holistic understanding of well-being. However, it is still challenging to achieve consistent and reliable real-time estimates of sleep stages using only smartwatches. This is especially true for individuals with irregular sleep patterns or sleep disorders. A major contributing factor is the distinct lack of publicly accessible, large-scale datasets that allow researchers and engineers to validate their wearable sleep staging algorithms against a population with diverse sleep patterns. Here, we present DREAMT, _**D**_ ataset for _**R**_ eal-time sleep stage _**E**_ stim _ **A**_ tion using _**M**_ ultisensor wearable _**T**_ echnology, a new dataset collected from 100 participants, which includes high-resolution signals from a smartwatch, expert sleep technician-annotated sleep stage labels, and clinical metadata related to sleep health and disorders. 

Vision Transformers (ViTs) have evolved in the field of computer vision by transitioning traditional Convolutional Neural Networks (CNNs) into attention-based architectures. This architecture processes input images as sequences of patches. ViTs achieve enhanced performance in many tasks such as image classification and object detection due to their ability to capture global dependencies within input data. While their software implementations are widely adopted, deploying ViTs on hardware introduces several challenges. These include fault tolerance in the presence of hardware failures, real-time reliability, and high computational requirements. Permanent faults that are in processing elements, interconnections, or memory subsystems lead to incorrect computations and degrading system performance. This paper proposes a fault-tolerant hardware implementation of ViTs to overcome these challenges. This hardware implementation integrates real-time fault detection and recovery mechanisms. The architecture includes four primary units: patch embedding, encoder, decoder, and Multi Layer Perceptron (MLP) which are supported by fault-tolerant components such as lightweight recompute units, a centralized Built-In Self-Test (BIST), and a learning-based decision-making system using machine learning model 'decision tree'. These units are interconnected through a centralized global buffer for efficient data transfer, ensuring seamless operation even under fault conditions.