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Field-programmable gate arrays (FPGAs) provide an opportunity to co-design applications with hardware accelerators, yet they remain difficult to program. High-level synthesis (HLS) tools promise to raise the level of abstraction by compiling C or C++ to accelerator designs. Repurposing legacy software languages, however, requires complex heuristics to map imperative code onto hardware structures. We find that the black-box heuristics in HLS can be unpredictable: changing parameters in the program that should improve performance can counterintuitively yield slower and larger designs. This paper proposes a type system that restricts HLS to programs that can predictably compile to hardware accelerators. The key idea is to model consumable hardware resources with a time-sensitive affine type system that prevents simultaneous uses of the same hardware structure. We implement the type system in Dahlia, a language that compiles to HLS C++, and show that it can reduce the size of HLS parameter spaces while accepting Pareto-optimal designs.more » « less
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Reedy, D. ; Williams, J. B. ; Gaire, B. ; Gatton, A. ; Weller, M. ; Menssen, A. ; Bauer, T. ; Henrichs, K. ; Burzynski, Ph. ; Berry, B. ; et al ( , Physical Review A)
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Ji, Q. ; Afridi, K. K. ; Bauer, T. ; Giesbrecht, G. ; Hou, Y. ; Lal, A. ; Ni, D. ; Persaud, A. ; Qin, Z. ; Seidl, P. ; et al ( , Review of Scientific Instruments)