Optical phase-change materials have enabled nonvolatile programmability in integrated photonic circuits by leveraging a reversible phase transition between amorphous and crystalline states. To control these materials in a scalable manner on-chip, heating the waveguide itself via electrical currents is an attractive option which has been recently explored using various approaches. Here, we compare the heating efficiency, fabrication variability, and endurance of two promising heater designs which can be easily integrated into silicon waveguides—a resistive microheater using n-doped silicon and one using a silicon p-type/intrinsic/n-type (PIN) junction. Raman thermometry is used to characterize the heating efficiencies of these microheaters, showing that both devices can achieve similar peak temperatures but revealing damage in the PIN devices. Subsequent endurance testing and characterization of both device types provide further insights into the reliability and potential damage mechanisms that can arise in electrically programmable phase-change photonic devices.
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Neuromorphic computing has the great potential to enable faster and more energy‐efficient computing by overcoming the von Neumann bottleneck. However, most emerging nonvolatile memory (NVM)‐based artificial synapses suffer from insufficient precision, nonlinear synaptic weight update, high write voltage, and high switching latency. Moreover, the spatiotemporal dynamics, an important temporal component for cognitive computing in spiking neural networks (SNNs), are hard to generate with existing complementary metal–oxide–semiconductor (CMOS) devices or emerging NVM. Herein, a three‐terminal, Li
x WO3‐based electrochemical synapse (LiWES) is developed with low programming voltage (0.2 V), fast programming speed (500 ns), and high precision (1024 states) that is ideal for artificial neural networks applications. Time‐dependent synaptic functions such as paired‐pulse facilitation (PPF) and temporal filtering that are critical for SNNs are also demonstrated. In addition, by leveraging the spike‐encoded timing information extracted from the short‐term plasticity (STP) behavior in the LiWES, an SNNs model is built to benchmark the pattern classification performance of the LiWES, and the result indicates a large boost in classification performance (up to 128×), compared with those NO‐STP synapses. -
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Abstract The development of novel doping strategies compatible with high‐resolution patterning and low cost, large‐scale manufacturing is critical to the future development of electronic devices. Here, an approach to achieve nanoscale site‐specific doping of Si wafer using DNA as both the template and the dopant carrier is reported. Upon thermal treatment, the phosphorous atoms in the DNA diffuse into Si wafer, resulting in doping within the region right around the DNA template. A doping length of 30 nm is achieved for 10 s of thermal treatment at 1000 °C. Prototype field effect transistors are fabricated using the DNA‐doped Si substrate; the device characteristics confirmed that the Si is n‐doped. It is also shown that this approach can be extended to achieve both n‐type and p‐type site‐specific doping of Si by using DNA nanostructures to pattern self‐assembled monolayers. This work shows that the DNA template is a dual‐use template that can both pattern Si and deliver dopants.
