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Thickness-dependent reliability in 3D-Cap HfO2-based FeRAM capacitors has been studied. Results show endurance larger than 1011 cycles and >10 years of extrapolated retention time. A significant polarization gain was made possible due to trenched capacitors that enhanced the effective areas. A major cause of the endurance failure is the dielectric breakdown after numerous cycles, which is linked to the gate leakage currents. Our temperature-dependent study of I-V characteristics has revealed Fowler-Nordheim tunneling at low temperatures and Frenkel-Poole conduction at room-to-high temperatures as the culprits. Such findings will be helpful for future commercialization of this technology. 

Apparent ‘Negative Capacitance’ (NC) effects have been observed in some ferroelectric-dielectric (FE-DE) bilayers by pulse measurements, and the associated results have been published that claim to be direct evidence to support the quasi-static ‘negative capacitance’ (QSNC) idea. However, the ‘NC’ effects only occur when sufficiently high voltage is applied, and even exist in stand-alone FE capacitors. These results contradict the QSNC theory, as it predicts that once stabilized (requires a DE layer), the FE remains in the ‘NC’ state regardless of the applied voltage. In this letter, by the use of Nucleation-Limited-Switching (NLS) model, we present our results obtained from simulation of pulse measurements on samples that are similar to the published ones. The simulation results indicate that reverse polarization switching occurs upon the falling edge of the pulses, which leads to the apparent hysteresis-free NC effect. This work provides an alternative interpretation of the experimental results without invoking the QSNC theory. 

An optimization principle for ferroelectric FET (FeFET), centered around charge matching between the ferroelectric and its underlying semiconductor, is theoretically investigated. This letter shows that, by properly reducing the ferroelectric polarization charge and its background dielectric constant, charge matching can be improved to enable simultaneously: i) reduction of the interlayer and semiconductor electric fields during programming, reading, and retention, leading to prolonged endurance and retention; ii) improvement of the memory window; and iii) suppression of device-to-device variations by affording full polarization switching. These attributes provide an incentive for the presentation of the proposed guidelines for FeFET optimization as detailed in this letter.