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Command and control (C2) data links over cellular networks is envisioned to be a reliable communications modality for various types of missions for Unmanned Aircraft System (UAS). The planning of UAS traffic and the provision of cellular communication resources are cross-coupled decisions that should be analyzed together to understand the quality of service such a modality can provide that meets business needs. The key to effective planning is the accurate estimation of communication link quality and the resource usage for a given air traffic requirement. In this work, a simulation and modelling framework is developed that integrates two open-source simulation platforms, Repast Simphony and ns-3, to generate UAS missions over different geographical areas and simulates the provision of 4G/5G cellular network connectivity to support their C2 and mission data links. To the best of our knowledge, this is the first simulator that co-simulates air traffic and cellular network communications for UAS while leveraging standardized 3GPP propagation models and incorporating detailed management of communication channels (i.e., resource blocks) at the cellular base station level. Three experiments were executed to demonstrate how the integrated simulation platform can be used to provide guidelines in communication resource allocation, air traffic management, and mission safety management in beyond visual line of sight (BVLOS) operations. 

Log-Structured Merge-trees (LSM-trees) have been widely used in modern NoSQL systems. Due to their out-of-place update design, LSM-trees have introduced memory walls among the memory components of multiple LSM-trees and between the write memory and the buffer cache. Optimal memory allocation among these regions is non-trivial because it is highly workload-dependent. Existing LSM-tree implementations instead adopt static memory allocation schemes due to their simplicity and robustness, sacrificing performance. In this paper, we attempt to break down these memory walls in LSM-based storage systems. We first present a memory management architecture that enables adaptive memory management. We then present a partitioned memory component structure with new flush policies to better exploit the write memory to minimize the write cost. To break down the memory wall between the write memory and the buffer cache, we further introduce a memory tuner that tunes the memory allocation between these two regions. We have conducted extensive experiments in the context of Apache AsterixDB using the YCSB and TPC-C benchmarks and we present the results here.