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Magnetic Random-Access Memory (MRAM) based p-bit neuromorphic computing devices are garnering increasing interest as a means to compactly and efficiently realize machine learning operations in Restricted Boltzmann Machines (RBMs). When embedded within an RBM resistive crossbar array, the p-bit based neuron realizes a tunable sigmoidal activation function. Since the stochasticity of activation is dependent on the energy barrier of the MRAM device, it is essential to assess the impact of process variation on the voltage-dependent behavior of the sigmoid function. Other influential performance factors arise from varying energy barriers on power consumption requiring a simulation environment to facilitate the multi-objective optimization of device and network parameters. Herein, transportable Python scripts are developed to analyze the output variation under changes in device dimensions on the accuracy of machine learning applications. Evaluation with RBM circuits using the MNIST dataset reveal impacts and limits for processing variation of device fabrication in terms of the resulting energy vs. accuracy tradeoffs, and the resulting simulation framework is available via a Creative Commons license. 

In this paper, a probabilistic interpolation recoder (PIR) circuit is developed for deep belief networks (DBNs) with probabilistic spin logic (p-bit)-based neurons. To verify the functionality and evaluate the performance of the PIRs, we have implemented a 784 × 200 × 10 DBN circuit in SPICE for a pattern recognition application using the MNIST dataset. The PIR circuits are leveraged in the last hidden layer to interpolate the probabilistic output of the neurons, which are representing different output classes, through sampling the p-bit’s output values and then counting them in a defined sampling time window. The PIR circuit is proposed as an alternative for conventional interpolation methods which were based on using a resistor capacitor tank to integrate each neuron’s output, followed by an analog-to-digital converter to generate the digital output. The circuit simulation results of PIR circuit exhibit at least 54%, 81%, and 78% reductions in power, energy, and energy-error-product, respectively, compared to previous techniques, without using any of the area-consuming analog components in the interpolation circuit. In addition, PIR circuits provide an inherent single stuck at fault tolerant feature to mitigate both transient and permanent faults at the circuit’s output. Reliability properties of the PIR circuits for single stuck-at faults are shown to be enhanced relative to conventional interpolation without requiring hardware redundancy. 

This poster paper describes the authors’ single-year National Science Foundation (NSF) project DRL-1825007 titled, “DCL: Synthesis and Design Workshop on Digitally-Mediated Team Learning” which has been conducted as one of nine awards within NSF-18-017: Principles for the Design of Digital STEM Learning Environments. Beginning in September 2018, the project conducted the activities herein to deliver a three-day workshop on Digitally-Mediated Team Learning (DMTL) to convene, invigorate, and task interdisciplinary science and engineering researchers, developers, and educators to coalesce the leading strategies for digital team learning. The deliverable of the workshop is a White Paper composed to identify one-year, three-year, and five-year research and practice roadmaps for highly-adaptable environments for computer-supported collaborative learning within STEM curricula. As subject to the chronology of events, highlights of the White Paper’s outcomes will be showcased within the poster itself.