Search for: All records

Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to considerably different design quality and performance-power tradeoff. In general, the impact of HDL coding is not clear until logic synthesis or even layout is completed. However, running synthesis merely as a feedback for HDL code is computationally not economical especially in early design phases when the code needs to be frequently modified. Furthermore, in late stages of design convergence burdened with high-impact engineering change orders (ECO’s), design iterations become prohibitively expensive. To this end, we propose a machine learning approach to Verilog-based Register-Transfer Level (RTL) design assessment without going through the synthesis process. It would allow designers to quickly evaluate the performance-power tradeoff among different options of RTL designs. Experimental results show that our proposed technique achieves an average of 95% prediction accuracy in terms of post-placement analysis, and is 6 orders of magnitude faster than evaluation by running logic synthesis and placement. 

There is broad belief that preparing all students in preK-12 for a future in STEM involves integrating computing and computational thinking (CT) tools and practices. Through creating and examining rich “STEM+CT” learning environments that integrate STEM and CT, researchers are defining what CT means in STEM disciplinary settings. This interactive session brings together a diverse spectrum of leading STEM researchers to share how they operationalize CT, what integrated CT and STEM learning looks like in their curriculum, and how this learning is measured. It will serve as a rich opportunity for discussion to help advance the state of the field of STEM and CT integration. 

There is broad belief that preparing all students in preK-12 for a future in STEM involves integrating computing and computational thinking (CT) tools and practices. Through creating and examining rich “STEM+CT” learning environments that integrate STEM and CT, researchers are defining what CT means in STEM disciplinary settings. This interactive session brings together a diverse spectrum of leading STEM researchers to share how they operationalize CT, what integrated CT and STEM learning looks like in their curriculum, and how this learning is measured. It will serve as a rich opportunity for discussion to help advance the state of the field of STEM and CT integration.