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Human Activity Recognition SoC for AR/VR with Integrated Neural Sensing, AI Classifier and Chained Infrared Communication for Multi-chip Collaboration

https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185392

Wei, Yijie ; Chen, Xi ; Gu, Jie ( June 2023 , Symposium on VLSI Technology and Circuits)

Free, publicly-accessible full text available June 1, 2024
Human emotion based real-time memory and computation management on resource-limited edge devices

https://doi.org/10.1145/3489517.3530490

Wei, Yijie ; Zhong, Zhiwei ; Gu, Jie ( July 2022 , ACM)
A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition

https://doi.org/10.1109/CICC53496.2022.9772838

Wei, Yijie ; Chen, Xi ; Gu, Jie ( April 2022 , Custom Integrated Circuit Conference)

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A Gesture Classification SoC for Rehabilitation With ADC-Less Mixed-Signal Feature Extraction and Training Capable Neural Network Classifier

https://doi.org/10.1109/JSSC.2020.3041288

Wei, Yijie ; Cao, Qiankai ; Otseidu, Kofi ; Hargrove, Levi J. ; Gu, Jie ( March 2021 , IEEE Journal of Solid-State Circuits)
null (Ed.)
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A Wearable Bio-signal Processing System with Ultra-low-power SoC and Collaborative Neural Network Classifier for Low Dimensional Data Communication

https://doi.org/10.1109/EMBC44109.2020.9176647

Wei, Yijie ; Cao, Qiankai ; Hargrove, Levi ; Gu, Jie ( July 2020 , Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC))

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A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training

https://doi.org/10.1109/CICC48029.2020.9075910

Wei, Yijie ; Cao, Qiankai ; Otseidu, Kofi ; Hargrove, Levi ; Gu, Jie ( March 2020 , Custom Integrated Circuits Conference)

An ultra-low-power gesture and gait classification SoC is presented for rehabilitation application featuring (1) mixed-signal feature extraction and integrated low-noise amplifier eliminating expensive ADC and digital feature extraction, (2) an integrated distributed deep neural network (DNN) ASIC supporting a scalable multi-chip neural network for sensor fusion with distortion resiliency for low-cost front end modules, (3) onchip learning of DNN engine allowing in-situ training of user specific operations. A 12-channel 65nm CMOS test chip was fabricated with 1μW power per channel, less than 3ms computation latency, on-chip training for user-specific DNN model and multi-chip networking capability.
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Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-Low Power SoC

https://doi.org/10.1109/DAC18072.2020.9218583

Wei, Yijie ; Otseidu, Kofi ; Gu, Jie ( January 2020 , Design Automation Conference)

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