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Low-Latency Parallel Row-Layered Min-sum MDPC Decoder for McEliece Cryptosystem

https://doi.org/10.1109/SiPS62058.2024.00034

Cai, Jiaxuan; Zhang, Xinmiao (November 2024, IEEE)

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Hardware Circuits and Systems Design for Post-Quantum Cryptography—A Tutorial Brief

https://doi.org/10.1109/TCSII.2024.3357836

Xie, Jiafeng; Zhao, Wenfeng; Lee, Hanho; Roy, Debapriya Basu; Zhang, Xinmiao (March 2024, IEEE Transactions on Circuits and Systems II: Express Briefs)
Low-Complexity Parallel Min-Sum Medium-Density Parity-Check Decoder for McEliece Cryptosystem

https://doi.org/10.1109/TCSI.2023.3319358

Cai, Jiaxuan; Zhang, Xinmiao (December 2023, IEEE Transactions on Circuits and Systems I: Regular Papers)

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Sparsity-Aware Medium-Density Parity-Check Decoder for McEliece Cryptosystems

https://doi.org/10.1109/TCSII.2023.3264578

Zhang, Xinmiao; Xie, Zhenshan (September 2023, IEEE Transactions on Circuits and Systems II: Express Briefs)

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Efficient Check Node Processing for Min-Max NB-LDPC Decoding over Lower-Order Finite Fields

https://doi.org/10.1109/ISCAS48785.2022.9937813

Zhang, Xinmiao (May 2022, IEEE)

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A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

https://doi.org/10.1109/COMST.2021.3126127

Ferraz, O.; Subramaniyan, S.; Chinthalaa, R.; Andrade, J.; Cavallaro, J. R.; Nandy, S. K.; Silva, V.; Zhang, X.; Falcao, G. (November 2021, IEEE Communications surveys and tutorials)

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