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Stochastic computing (SC) is a reemerging computing paradigm that oers low-cost and noise-resilient hardware designs for a variety of arithmetic functions. In SC, circuits operate on uniform bit-streams, where the value is encoded by the probability of observing ‘1’s in the stream. The accuracy of SC operations highly depends on the correlation between input bit-streams. Some operations, such as minimum and maximum, require highly correlated inputs, whereas others like multiplication demand uncorrelated or statistically independent inputs for accurate results. Developing low-cost and accurate correlation manipulation circuits is critical, as they allow correlation management without incurring the high cost of bit-stream regeneration. This work introduces novel in-stream correlator and decorrelator circuits capable of: 1) adjusting correlation between stochastic bit-streams and 2) controlling the distribution of ‘1’s in the output bit-streams. Compared to state-of-the-art (SoA) approaches, our designs oer improved accuracy and reduced hardware overhead. The output bit-streams enjoy low-discrepancy (LD) distribution, leading to higher quality of results. To further increase the accuracy when dealing with pseudo-random inputs, we propose an enhancement module that balances the number of ‘1’s across adjacent input segments. We show the eectiveness of the proposed techniques through two application case studies: SC design of sorting and median filtering. 

Sorting is a fundamental operation in various applications and a traditional research topic in computer science. Improving the performance of sorting operations can have a significant impact on many application domains. Much attention has been paid to hardware-based solutions for high-performance sorting. These are often realized with application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Recently, in-memory sorting solutions have also been proposed to address the movement cost issue between memory and processing units, also known as the Von Neumann bottleneck. Due to the complexity of the sorting algorithms, achieving an efficient hardware implementation for sorting data is challenging. A large body of prior solutions is built on compare-and-swap (CAS) units. These are categorized ascomparison-basedsorting. Some recent solutions offercomparison-freesorting. In this survey, we review the latest works in the area of hardware-based sorting. We also discuss the recent hardware solutions forpartialandstreamsorting. Finally, we discuss some important concerns that need to be considered in the future designs of sorting systems. 

Quantum image processing (QIP) is an emerging field that integrates image processing with the principles of quantum computing (QC). As quantum technologies advance, researchers face new opportunities and challenges in developing efficient QIP techniques. This paper provides an overview of quantum image representations, with a focus on two prominent encoding schemes: Novel Enhanced Quantum Representation (NEQR) and Fourier-based Quantum Image Representation (FRQI). We compare their performance in noisy quantum environments by evaluating qubit requirements, image quality, and computational efficiency. The study further analyzes the impact of quantum gate errors and qubit limitations on image reconstruction fidelity. We also compare GPU and QPU performance to highlight their strengths and weaknesses. Our findings stress the importance of error mitigation, advancements in quantum hardware, and the advancements of quantum-classical hybrid systems to drive future progress in QIP. 

Inspired by the human brain, Hyperdimensional Computing (HDC) processes information efficiently by operating in high-dimensional space using hypervectors. While previous works focus on optimizing pre-generated hypervectors in software, this study introduces a novel on-the-fly vector generation method in hardware with O(1) complexity, compared to the O(N) iterative search used in conventional approaches to find the best orthogonal hypervectors. Our approach leverages Hadamard binary coefficients and unary computing to simplify encoding into addition-only operations after the generation stage in ASIC, implemented using in-memory computing. The proposed design significantly improves accuracy and computational efficiency across multiple benchmark datasets.