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  1. Abstract The transition towards designs which co-package electronic and photonic die together in data center switch packages has created a scaling path to Petabyte per second (Pbps) input/output (I/O) in such systems. In a co-packaged design, the scaling of bandwidth, cost, and energy will be governed by the number of optical I/O channels and the data rate per channel. While optical communication provide an opportunity to exploit wavelength division multiplexing to scale data rate, the limited 127 µm pitch of V-groove based single mode fiber arrays and the use of active alignment and bonding for their packaging present challenges to scaling the number of optical channels. Flip-chip optical couplers which allow for low loss, broadband operation and automated passive assembly represent a solution for continued scaling. In this paper, we propose a novel scheme to vertically couple between silicon based waveguides on separate chips using graded index couplers in combination with an evanescent coupler. Simulation results using a 3D finite-difference time-domain solver are presented, demonstrating coupling losses as low as 0.35 dB for a chip-to-chip gap of 11 µm; 1 dB vertical and lateral alignment tolerances of approximately 2.45 µm and ± 2.66 µm, respectively; and a possible 1 dB bandwidth of greater than 1500 nm. These results demonstrate the potential of our coupler as a universal interface in future co-packaged optics systems. 
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  2. Gregory, Groot; Heinz-Garcia, Jonathan (Ed.)
    Free, publicly-accessible full text available September 18, 2026
  3. Kallepalli, Akhil (Ed.)
    As the semiconductor and photonics industries grapple with mounting business pressures, weaving resourceefficiency into engineering education has evolved from a priority to an imperative. Under the umbrella of FUTUR-IC, this paper highlights novel pedagogical strategies at Bridgewater State University (BSU) aimed at equipping photonics and optical engineers to address today’s ecological challenges. We detail two complementary approaches that together form a cohesive educational framework. The first involves a newly introduced fresh year-level seminar on Resource Efficient Microchip Manufacturing, which immerses students in resource-efficiency metrics such as Life Cycle Intelligence and “design for resourceefficiency” principles. By interlinking photonic integration concepts with tangible business impact assessments, this course fosters an early appreciation of how advanced technologies can be developed responsibly, with reduced energy consumption and minimized waste. The second approach redefines senior-level engineering design courses to embed multifaceted resourceefficiency criteria in the design process. Through project-based learning and collaboration with industry partners, students integrate photonic solutions with data-driven metrics, refining their ability to propose holistic prototypes. These initiatives go beyond technical mastery to cultivate interdisciplinary collaboration and critical thinking. This work illustrates how an integrated approach to engineering education can spark the next generation of practitioners to design for both technological excellence and business viability. 
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    Free, publicly-accessible full text available July 7, 2026
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  6. Free, publicly-accessible full text available February 1, 2026