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Award ID contains: 2447566

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  1. ; ; ; (, ACM)
    Free, publicly-accessible full text available May 6, 2026
  2. ; ; ; (, IEEE)
    Free, publicly-accessible full text available November 18, 2025
  3. ; ; ; ; ; (, IEEE)
    Free, publicly-accessible full text available November 2, 2025
  4. ; ; ; ; (, IEEE)
    Full Text Available 
  5. ; ; (, IEEE)
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  6. ; ; (, Micromachines)
    This paper conducts a comprehensive study on intermittent computing within IoT environments, emphasizing the interplay between different dataflows—row, weight, and output—and a variety of non-volatile memory technologies. We then delve into the architectural optimization of these systems using a spatial architecture, namely IDEA, with their processing elements efficiently arranged in a rhythmic pattern, providing enhanced performance in the presence of power failures. This exploration aims to highlight the diverse advantages and potential applications of each combination, offering a comparative perspective. In our findings, using IDEA for the row stationary dataflow with AlexNet on the CIFAR10 dataset, we observe a power efficiency gain of 2.7% and an average reduction of 21% in the required cycles. This study elucidates the potential of different architectural choices in enhancing energy efficiency and performance in IoT systems. 
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