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1. SCV-GNN: Sparse Compressed Vector-based Graph Neural Network Aggregation

   https://doi.org/10.1109/TCAD.2023.3291672  

   Unnikrishnan, Nanda K.; Gould, Joe; Parhi, Keshab K. (July 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)

   Graph neural networks (GNNs) have emerged as a powerful tool to process graph-based data in fields like communication networks, molecular interactions, chemistry, social networks, and neuroscience. GNNs are characterized by the ultra-sparse nature of their adjacency matrix that necessitates the development of dedicated hardware beyond general-purpose sparse matrix multipliers. While there has been extensive research on designing dedicated hardware accelerators for GNNs, few have extensively explored the impact of the sparse storage format on the efficiency of the GNN accelerators. This paper proposes SCV-GNN with the novel sparse compressed vectors (SCV) format optimized for the aggregation operation. We use Z-Morton ordering to derive a data-locality-based computation ordering and partitioning scheme. The paper also presents how the proposed SCV-GNN is scalable on a vector processing system. Experimental results over various datasets show that the proposed method achieves a geometric mean speedup of 7.96× and 7.04× over CSC and CSR aggregation operations, respectively. The proposed method also reduces the memory traffic by a factor of 3.29× and 4.37× over compressed sparse column (CSC) and compressed sparse row (CSR), respectively. Thus, the proposed novel aggregation format reduces the latency and memory access for GNN inference. 

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2. RED: A ReRAM-based Efficient Accelerator for Deconvolutional Computation

   https://doi.org/10.1109/TCAD.2020.2981055  

   Li, Ziru; Li, Bing; Fan, Zichen; Li, Hai (March 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)

   Deconvolution is a key component in contemporary neural networks, especially generative adversarial networks (GANs) and fully convolutional networks (FCNs). Due to extra operations of deconvolution compared to convolution, considerable degradation of performance as well as energy efficiency is incurred when implementing deconvolution on the existing resistive random access memory (ReRAM)-based processing-in-memory (PIM) accelerators. In this work, we propose a ReRAM-based accelerator design, RED, for providing high-performance and low-energy deconvolution. We analyze the deconvolution execution on the existing ReRAM-based PIMs and utilize its interior computation pattern for design optimization. RED includes two major contributions: pixel-wise mapping scheme and zero-skipping data flow. Pixel-wise mapping scheme removes the zero insertion and performs convolutions over several ReRAM arrays and thus enables parallel computations with non-zero inputs. Zero-skipping data flow, assisted with customized input buffers design, enhances the computation parallelism and input data reuse. In evaluation, we compare RED against the existing ReRAM-based PIMs and CMOS-based counterpart with a variety of GAN and FCN models, each of which contains multiple deconvolution layers. The experimental results show that RED achieves a 4.0×-56.16× speedup and a 1.05×-18.17× energy efficiency improvement over previous related accelerator designs. 

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3. PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks

   https://doi.org/10.1109/ICCD.2018.00048  

   Rakin, Adnan Siraj; Angizi, Shaahin; He, Zhezhi; Fan, Deliang (October 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD))

   Generative Adversarial Network (GAN) has emerged as one of the most promising semi-supervised learning methods where two neural nets train themselves in a competitive environment. In this paper, as far as we know, we are the first to present a statistically trained Ternarized Generative Adversarial Network (TGAN) with fully ternarized weights (i.e. -1,0,+1) to massively reduce the need for computation and storage resources in the conventional GAN structures. In the proposed TGAN, the computationally expensive convolution operations (i.e. Multiplication and Accumulation) in both generator and discriminator's forward path are converted into hardware-friendly Addition/Subtraction operations. Accordingly, we propose a Processing-in-Memory accelerator for TGAN called (PIM-TGAN) based on Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM) computational sub-arrays to efficiently accelerate the training process of GAN within non-volatile memory. In addition, we propose a parallelism technique to further enhance the training efficiency of TGAN. Our device-to-architecture co-simulation results show that, with almost the same inception score to the baseline GAN with floating point number weights on different data-sets, the proposed PIM-TGAN can obtain ~25.6× better energy-efficiency and 22× speedup compared to GPU platform averagely, and, 9.2× better energy-efficiency and 5.4× speedup over the best processing-in-ReRAM accelerators. 

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4. ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM

   https://doi.org/10.23919/DATE48585.2020.9116422  

   Wang, Yitu; Chen, Fan; Song, Linghao; Richard Shi, C. -J.; Li, Hai Helen; Chen, Yiran (March 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE))

   Deep neural networks (DNNs) emerge as a key component in various applications. However, the ever-growing DNN size hinders efficient processing on hardware. To tackle this problem, on the algorithmic side, compressed DNN models are explored, of which block-circulant DNN models are memory efficient and hardware-friendly; on the hardware side, resistive random-access memory (ReRAM) based accelerators are promising for in-situ processing of DNNs. In this work, we design an accelerator named ReBoc for accelerating block-circulant DNNs in ReRAM to reap the benefits of light-weight models and efficient in-situ processing simultaneously. We propose a novel mapping scheme which utilizes Horizontal Weight Slicing and Intra-Crossbar Weight Duplication to map block-circulant DNN models onto ReRAM crossbars with significant improved crossbar utilization. Moreover, two specific techniques, namely Input Slice Reusing and Input Tile Sharing are introduced to take advantage of the circulant calculation feature in block- circulant DNNs to reduce data access and buffer size. In REBOC, a DNN model is executed within an intra-layer processing pipeline and achieves respectively 96× and 8.86× power efficiency improvement compared to the state-of-the-art FPGA and ASIC accelerators for block-circulant neural networks. Compared to ReRAM-based DNN accelerators, REBOC achieves averagely 4.1× speedup and 2.6× energy reduction. 

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5. Variation-Aware Memristor-Based Analog Accelerator for Vision Transformer

   https://doi.org/10.3390/electronics15051116  

   Qu, Qianhou; Lu, Sheng; Shang, Liuting; Jung, Sungyong; Liang, Qilian; Pan, Chenyun (March 2026, Electronics)

   Vision transformers (ViTs) have emerged as one of the most popular computer vision models, achieving remarkable performance in image recognition. However, ViTs require large-scale, high-dimensional matrix computations, and traditional digital accelerators, such as graphics processing units (GPUs), have memory bandwidth limitations, leading to higher latency, increased energy consumption, and larger area. To address this challenge, this paper proposes a memristor-based analog accelerator that leverages memristor crossbar arrays for in-memory computing, reducing data movement and improving computational efficiency. Considering the non-ideal characteristics of memristor devices and the influence of analog circuitry, we incorporate Gaussian-distributed analog computation error at each step and memristor non-ideality modeling into the ViT inference to enable realistic evaluation under hardware-level conditions. Experimental evaluation on ImageNet-1k dataset with TIMM-pretrained ViT models shows that the proposed analog accelerator can achieve the same Top-1 accuracy as a custom-designed 5 nm digital baseline accelerator, even with ~35% analog computation error and ~10% memristor conductance variation injected at each step. Compared to the digital counterpart, the proposed design achieves an 11.9× reduction in energy-delay product (EDP) and a 137.2× reduction in energy-delay-area product (EDAP). 

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