Motivated by the significantly higher cost of writing than reading in emerging memory technologies, we consider parallel algorithm design under such asymmetric read-write costs, with the goal of reducing the number of writes while preserving work-efficiency and low span. We present a nested-parallel model of computation that combines (i) small per-task stack-allocated memories with symmetric read-write costs and (ii) an unbounded heap-allocated shared memory with asymmetric read-write costs, and show how the costs in the model map efficiently onto a more concrete machine model under a work-stealing scheduler. We use the new model to design reduced write, work-efficient, low span parallel algorithms for a number of fundamental problems such as reduce, list contraction, tree contraction, breadth-first search, ordered filter, and planar convex hull. For the latter two problems, our algorithms are output-sensitive in that the work and number of writes decrease with the output size. We also present a reduced write, low span minimum spanning tree algorithm that is nearly work-efficient (off by the inverse Ackermann function). Our algorithms reveal several interesting techniques for significantly reducing shared memory writes in parallel algorithms without asymptotically increasing the number of shared memory reads.
Parallel Write-Efficient Algorithms and Data Structures for Computational Geometry
In this paper, we design parallel write-efficient geometric algorithms
that perform asymptotically fewer writes than standard
algorithms for the same problem. This is motivated by emerging
non-volatile memory technologies with read performance being
close to that of random access memory but writes being significantly
more expensive in terms of energy and latency. We design
algorithms for planar Delaunay triangulation, k-d trees, and static
and dynamic augmented trees. Our algorithms are designed in
the recently introduced Asymmetric Nested-Parallel Model, which
captures the parallel setting in which there is a small symmetric
memory where reads and writes are unit cost as well as a large
asymmetric memory where writes are ω times more expensive
than reads. In designing these algorithms, we introduce several
techniques for obtaining write-efficiency, including DAG tracing,
prefix doubling, and α-labeling, which we believe will be useful for
designing other parallel write-efficient algorithms.
- Award ID(s):
- 1533858
- Publication Date:
- NSF-PAR ID:
- 10080526
- Journal Name:
- ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)
- Volume:
- 30
- Page Range or eLocation-ID:
- 235 to 246
- Sponsoring Org:
- National Science Foundation
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Accepted Manuscript1.0
- Publisher's Version of Record
- https://doi.org/10.1145/3210377.3210380
