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1. Analyzing Cache Side Channels Using Deep Neural Networks

   https://doi.org/10.1145/3274694.3274715  

   Zhang, Tianwei; Zhang, Yinqian; Lee, Ruby B. (December 2018, 34th Annual Computer Security Applications Conference (ACSAC))

   null (Ed.)

   Cache side-channel attacks aim to breach the confidentiality of a computer system and extract sensitive secrets through CPU caches. In the past years, different types of side-channel attacks targeting a variety of cache architectures have been demonstrated. Meanwhile, different defense methods and systems have also been designed to mitigate these attacks. However, quantitatively evaluating the effectiveness of these attacks and defenses has been challenging. We propose a generic approach to evaluating cache side-channel attacks and defenses. Specifically, our method builds a deep neural network with its inputs as the adversary's observed information, and its outputs as the victim's execution traces. By training the neural network, the relationship between the inputs and outputs can be automatically discovered. As a result, the prediction accuracy of the neural network can serve as a metric to quantify how much information the adversary can obtain correctly, and how effective a defense solution is in reducing the information leakage under different attack scenarios. Our evaluation suggests that the proposed method can effectively evaluate different attacks and defenses. 

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2. Kobold: Simplified Cache Coherence for Cache-Attached Accelerators

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3. Cache-Out: Leaking Cache Memory Using Hardware Trojan

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   Khan, Mohammad Nasim; De, Asmit; Ghosh, Swaroop (June 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems)
4. Cache automaton

   https://doi.org/10.1145/3123939.3123986  

   Subramaniyan, Arun; Wang, Jingcheng; Balasubramanian, Ezhil R.; Blaauw, David; Sylvester, Dennis; Das, Reetuparna (October 2017, MICRO-50 '17 Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture)

   Finite State Automata are widely used to accelerate pattern matching in many emerging application domains like DNA sequencing and XML parsing. Conventional CPUs and compute-centric accelerators are bottlenecked by memory bandwidth and irregular memory access patterns in automata processing. We present Cache Automaton, which repurposes last-level cache for automata processing, and a compiler that automates the process of mapping large real world Non-Deterministic Finite Automata (NFAs) to the proposed architecture. Cache Automaton extends a conventional last-level cache architecture with components to accelerate two phases in NFA processing: state-match and state-transition. State-matching is made efficient using a sense-amplifier cycling technique that exploits spatial locality in symbol matches. State-transition is made efficient using a new compact switch architecture. By overlapping these two phases for adjacent symbols we realize an efficient pipelined design. We evaluate two designs, one optimized for performance and the other optimized for space, across a set of 20 diverse benchmarks. The performance optimized design provides a speedup of 15× over DRAM-based Micron's Automata Processor and 3840× speedup over processing in a conventional x86 CPU. The proposed design utilizes on an average 1.2MB of cache space across benchmarks, while consuming 2.3nJ of energy per input symbol. Our space optimized design can reduce the cache utilization to 0.72MB, while still providing a speedup of 9× over AP. 

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5. ReViCe: Reusing Victim Cache to Prevent Speculative Cache Leakage

   https://doi.org/10.1109/SecDev45635.2020.00029  

   Kim, Sungkeun; Mahmud, Farabi; Huang, Jiayi; Majumder, Pritam; Christou, Neophytos; Muzahid, Abdullah; Tsai, Chia-Che; Kim, Eun Jung (September 2020, IEEE Secure Development (SecDev))