Cui, Jinhua, Zhang, Youtao, Wu, Weiguo, Yang, Jun, Wang, Yinfeng, and Huang, Jianhang. DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems. Retrieved from https://par.nsf.gov/biblio/10087434. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37.8 Web. doi:10.1109/TCAD.2017.2766156.

Cui, Jinhua, Zhang, Youtao, Wu, Weiguo, Yang, Jun, Wang, Yinfeng, & Huang, Jianhang. DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37 (8). Retrieved from https://par.nsf.gov/biblio/10087434. https://doi.org/10.1109/TCAD.2017.2766156

Cui, Jinhua, Zhang, Youtao, Wu, Weiguo, Yang, Jun, Wang, Yinfeng, and Huang, Jianhang. "DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37 (8). Country unknown/Code not available. https://doi.org/10.1109/TCAD.2017.2766156. https://par.nsf.gov/biblio/10087434.

@article{osti_10087434,
place = {Country unknown/Code not available}, title = {DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems}, url = {https://par.nsf.gov/biblio/10087434}, DOI = {10.1109/TCAD.2017.2766156}, abstractNote = {}, journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, volume = {37}, number = {8}, author = {Cui, Jinhua and Zhang, Youtao and Wu, Weiguo and Yang, Jun and Wang, Yinfeng and Huang, Jianhang}, }