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In-Memory Computing (IMC) technology has been considered to be a promising approach to solve well-known memory-wall challenge for data intensive applications. In this paper, we are the first to propose MnM, a novel IMC system with innovative architecture/circuit designs for fast and efficient Min/Max searching computation in emerging Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM). Our proposed SOT-MRAM based in-memory logic circuits are specially optimized to perform parallel, one-cycle XNOR logic that are heavily used in the Min/Max searching-in-memory algorithm. Our novel in-memory XNOR circuit also has an overhead of just two transistors per row when compared to most prior methodologies which typically use multiple sense amplifiers or complex CMOS logic gates. We also design all other required peripheral circuits for implementing complete Min/Max searching-in-MRAM computation. Our cross-layer comprehensive experiments on Dijkstra's algorithm and other sorting algorithms in real word datasets show that our MnM could achieve significant performance improvement over CPUs, GPUs, and other competing IMC platforms based on RRAM/MRAM/DRAM.
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A Single-Device Embodiment of XNOR Logic: TransiXNOR
In this work, a single-device embodiment of XNOR logic, TransiXNOR, is designed and simulated. With double gates controlling the current tunneling plane either at the source or at the drain, the TransiXNOR is ON if and only if the dual gates are biased at both high or low voltage, thus the XNOR logic.
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- Award ID(s):
- 1740286
- PAR ID:
- 10107786
- Date Published:
- Journal Name:
- Device Research Conference
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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