Abstract We present a novel photonic chip design for high bandwidth four-degree optical switches that support high-dimensional switching mechanisms with low insertion loss and low crosstalk in a low power consumption level and a short switching time. Such four-degree photonic chips can be used to build an integrated full-grid Photonic-on-Chip Network (PCN). With four distinct input/output directions, the proposed photonic chips are superior compared to the current bidirectional photonic switches, where a conventionally sizable PCN can only be constructed as a linear chain of bidirectional chips. Our four-directional photonic chips are more flexible and scalable for the design of modern optical switches, enabling the construction of multi-dimensional photonic chip networks that are widely applied for intra-chip communication networks and photonic data centers. More noticeably, our photonic networks can be self-controlling with our proposed Multi-Sample Discovery model, a deep reinforcement learning model based on Proximal Policy Optimization. On a PCN, we can optimize many criteria such as transmission loss, power consumption, and routing time, while preserving performance and scaling up the network with dynamic changes. Experiments on simulated data demonstrate the effectiveness and scalability of the proposed architectural design and optimization algorithm. Perceivable insights make the constructed architecture become the self-controlling photonic-on-chip networks.
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WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs
Photonic Network-on-Chips (PNoCs) offer promising benefits over Electrical Network-on-Chips (ENoCs) in many-core systems owing to their lower latencies, higher bandwidth, and lower energy-per-bit communication with negligible data-dependent power. These benefits, however, are limited by a number of challenges. Microring resonators (MRRs) that are used for photonic communication have high sensitivity to process variations and on-chip thermal variations, giving rise to possible resonant wavelength mismatches. State-of-the-art microheaters, which are used to tune the resonant wavelength of MRRs, have poor efficiency resulting in high thermal tuning power. In addition, laser power and high static power consumption of drivers, serializers, comparators, and arbitration logic partially negate the benefits of the sub-pJ operating regime that can be obtained with PNoCs. To reduce PNoC power consumption, this paper introduces WAVES, a wavelength selection technique to identify and activate the minimum number of laser wavelengths needed, depending on an application's bandwidth requirement. Our results on a simulated 2.5D manycore system with PNoC demonstrate an average of 23% (resp. 38%) reduction in PNoC power with only <;1% (resp. <;5%) loss in system performance.
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- Award ID(s):
- 1716352
- NSF-PAR ID:
- 10112265
- Date Published:
- Journal Name:
- Design Automation and Test in Europe
- Page Range / eLocation ID:
- 516 to 521
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Abstract Silicon microring resonators (Si-MRRs) play essential roles in on-chip wavelength division multiplexing (WDM) systems due to their ultra-compact size and low energy consumption. However, the resonant wavelength of Si-MRRs is very sensitive to temperature fluctuations and fabrication process variation. Typically, each Si-MRR in the WDM system requires precise wavelength control by free carrier injection using PIN diodes or thermal heaters that consume high power. This work experimentally demonstrates gate-tuning on-chip WDM filters for the first time with large wavelength coverage for the entire channel spacing using a Si-MRR array driven by high mobility titanium-doped indium oxide (ITiO) gates. The integrated Si-MRRs achieve unprecedented wavelength tunability up to 589 pm/V, or VπL of 0.050 V cm with a high-quality factor of 5200. The on-chip WDM filters, which consist of four cascaded ITiO-driven Si-MRRs, can be continuously tuned across the 1543–1548 nm wavelength range by gate biases with near-zero power consumption.
- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.23919/DATE.2019.8715036
