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1. Self-controlling photonic-on-chip networks with deep reinforcement learning

   https://doi.org/10.1038/s41598-021-02583-7  

   Do, Nguyen ; Truong, Dung ; Nguyen, Duy ; Hoai, Minh ; Pham, Cuong ( December 2021 , Scientific Reports)

   Abstract We present a novel photonic chip design for high bandwidth four-degree optical switches that support high-dimensional switching mechanisms with low insertion loss and low crosstalk in a low power consumption level and a short switching time. Such four-degree photonic chips can be used to build an integrated full-grid Photonic-on-Chip Network (PCN). With four distinct input/output directions, the proposed photonic chips are superior compared to the current bidirectional photonic switches, where a conventionally sizable PCN can only be constructed as a linear chain of bidirectional chips. Our four-directional photonic chips are more flexible and scalable for the design of modern optical switches, enabling the construction of multi-dimensional photonic chip networks that are widely applied for intra-chip communication networks and photonic data centers. More noticeably, our photonic networks can be self-controlling with our proposed Multi-Sample Discovery model, a deep reinforcement learning model based on Proximal Policy Optimization. On a PCN, we can optimize many criteria such as transmission loss, power consumption, and routing time, while preserving performance and scaling up the network with dynamic changes. Experiments on simulated data demonstrate the effectiveness and scalability of the proposed architectural design and optimization algorithm. Perceivable insights make the constructed architecture become the self-controllingmore »photonic-on-chip networks.« less
2. Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study

   https://doi.org/10.1145/3487365  

   Karempudi, Venkata Sai ; Sunny, Febin ; Thakkar, Ishan G. ; Chittamuru, Sai Vineel ; Nikdast, Mahdi ; Pasricha, Sudeep ( July 2022 , ACM Journal on Emerging Technologies in Computing Systems)

   Photonic network-on-chip (PNoC) architectures employ photonic links with dense wavelength-division multiplexing (DWDM) to enable high throughput on-chip transfers. Unfortunately, increasing the DWDM degree (i.e., using a larger number of wavelengths) to achieve a higher aggregated data rate in photonic links and, hence, higher throughput in PNoCs, requires sophisticated and costly laser sources along with extra photonic hardware. This extra hardware can introduce undesired noise to the photonic link and increase the bit error rate (BER), power, and area consumption of PNoCs. To mitigate these issues, the use of 4-pulse amplitude modulation (4-PAM) signaling, instead of the conventional on-off keying (OOK) signaling, can halve the wavelength signals utilized in photonic links for achieving the target aggregate data rate while reducing the overhead of crosstalk noise, BER, and photonic hardware. There are various designs of 4-PAM modulators reported in the literature. For example, the signal superposition (SS)–, electrical digital-to-analog converter (EDAC)–, and optical digital-to-analog converter (ODAC)–based designs of 4-PAM modulators have been reported. However, it is yet to be explored how these SS-, EDAC-, and ODAC-based 4-PAM modulators can be utilized to design DWDM-based photonic links and PNoC architectures. In this article, we provide a systematic analysis of the SS, EDAC, andmore »ODAC types of 4-PAM modulators from prior work with regards to their applicability and utilization overheads. We then present a heuristic-based search method to employ these 4-PAM modulators for designing DWDM-based SS, EDAC, and ODAC types of 4-PAM photonic links with two different design goals: (i) to attain the desired BER of 10 -9 at the expense of higher optical power and lower aggregate data rate and (ii) to attain maximum aggregate data rate with the desired BER of 10 -9 at the expense of longer packet transfer latency. We then employ our designed 4-PAM SS–, 4-PAM EDAC–, 4-PAM ODAC–, and conventional OOK modulator–based photonic links to constitute corresponding variants of the well-known CLOS and SWIFT PNoC architectures. We eventually compare our designed SS-, EDAC-, and ODAC-based variants of 4-PAM links and PNoCs with the conventional OOK links and PNoCs in terms of performance and energy efficiency in the presence of inter-channel crosstalk. From our link-level and PNoC-level evaluation, we have observed that the 4-PAM EDAC–based variants of photonic links and PNoCs exhibit better performance and energy efficiency compared with the OOK-, 4-PAM SS–, and 4-PAM ODAC–based links and PNoCs.« less
3. Opportunities for Cross-Layer Design in High-Performance Computing Systems with Integrated Silicon Photonic Networks

   https://doi.org/978-3-9819263-4-7  

   Mirza, A. ; Avari, S. ; Taheri, E. ; Pasricha, S. ; Nikdast, M. ( March 2020 , IEEE/ACM Design, Automation and Test in Europe (DATE) Conference and Exhibition)

   With the ever growing complexity of high performance computing (HPC) systems to satisfy emerging application requirements (e.g., high memory bandwidth requirement for machine learning applications), the performance bottleneck in such systems has moved from being computation-centric to be more communication-centric. Silicon photonic interconnection networks have been proposed to address the aggressive communication requirements in HPC systems, to realize higher bandwidth, lower latency, and better energy efficiency. There have been many successful efforts on developing silicon photonic devices, integrated circuits, and architectures for HPC systems. Moreover, many efforts have been made to address and mitigate the impact of different challenges (e.g., fabrication process and thermal variations) in silicon photonic interconnects. However, most of these efforts have focused only on a single design layer in the system design space (e.g., device, circuit or architecture level). Therefore, there is often a gap between what a design technique can improve in one layer, and what it might impair in another one. In this paper, we discuss the promise of cross-layer design methodologies for HPC systems integrating silicon photonic interconnects. In particular, we discuss how such cross-layer design solutions based on cooperatively designing and exchanging design objectives among different system design layers can help achievemore »the best possible performance when integrating silicon photonics into HPC systems« less
4. A 65nm Resonant Electro-Quasistatic 5-240uW Human Whole-Body Powering and 2.19uW Communication SoC with Automatic Maximum Resonant Power Tracking

   https://doi.org/10.1109/CICC51472.2021.9431456  

   Modak, Nirmoy ; Das, Debayan ; Nath, Mayukh ; Chatterjee, Baibhab ; Gaurav Kumar, K ; Maity, Shovan ; Sen, Shreyas ( April 2021 , 2021 IEEE Custom Integrated Circuits Conference (CICC))

   Applications like Connected Healthcare through physiological signal monitoring and Secure Authentication using wearable keys can benefit greatly from battery-less operation. Low power communication along with energy harvesting is critical to sustain such perpetual battery-less operation. Previous studies have used techniques such as Tribo-Electric, Piezo-Electric, RF energy harvesting for Body Area Network devices, but they are restricted to on-body node placements. Human body channel is known to be a promising alternative to wireless radio wave communication for low power operation [1-4], through Human Body Communication, as well as very recently as a medium for power transfer through body coupled power transfer [5]. However, channel length (L) dependency of the received power makes it inefficient for L>40cm. There have also been a few studies for low power communication through the human body, but none of them could provide sustainable battery-less operation. In this paper, we utilize Resonant Electro Quasi-Static Human Body Communication (Res-EQS HBC) with Maximum Resonance Power Tracking (MRPT) to enable channel length independent whole-body communication and powering (Fig.1). We design the first system to simultaneously transfer Power and Data between a HUB device and a wearable through the human body to enable battery-less operation. Measurement results show 240uW, 28uW andmore »5uW power transfer through the body in a MachineMachine (large devices with strong ground connection) Tabletop (small devices kept on a table, as in [5]) and Wearable-Wearable (small form factor battery operated devices) scenario respectively, independent of body channel length, while enabling communication with a power consumption of only 2.19uW. This enables >25x more power transfer with >100x more efficiency compared to [5] for Tabletop and 100cm Body distance by utilizing the benefits of EQS. The MRPT loop automatically tracks device and posture dependent resonance point changes to maximize power transfer in all cases.« less
5. Silicon nitride stress-optic microresonator modulator for optical control applications

   https://doi.org/10.1364/OE.467721  

   Wang, Jiawei ; Liu, Kaikai ; Harrington, Mark W. ; Rudy, Ryan Q. ; Blumenthal, Daniel J. ( August 2022 , Optics Express)

   Modulation-based control and locking of lasers, filters and other photonic components is a ubiquitous function across many applications that span the visible to infrared (IR), including atomic, molecular and optical (AMO), quantum sciences, fiber communications, metrology, and microwave photonics. Today, modulators used to realize these control functions consist of high-power bulk-optic components for tuning, sideband modulation, and phase and frequency shifting, while providing low optical insertion loss and operation from DC to 10s of MHz. In order to reduce the size, weight and cost of these applications and improve their scalability and reliability, modulation control functions need to be implemented in a low loss, wafer-scale CMOS-compatible photonic integration platform. The silicon nitride integration platform has been successful at realizing extremely low waveguide losses across the visible to infrared and components including high performance lasers, filters, resonators, stabilization cavities, and optical frequency combs. Yet, progress towards implementing low loss, low power modulators in the silicon nitride platform, while maintaining wafer-scale process compatibility has been limited. Here we report a significant advance in integration of a piezo-electric (PZT, lead zirconate titanate) actuated micro-ring modulation in a fully-planar, wafer-scale silicon nitride platform, that maintains low optical loss (0.03 dB/cm in a 625 µmmore »resonator) at 1550 nm, with an order of magnitude increase in bandwidth (DC - 15 MHz 3-dB and DC - 25 MHz 6-dB) and order of magnitude lower power consumption of 20 nW improvement over prior PZT modulators. The modulator provides a >14 dB extinction ratio (ER) and 7.1 million quality-factor (Q) over the entire 4 GHz tuning range, a tuning efficiency of 162 MHz/V, and delivers the linearity required for control applications with 65.1 dB·Hz^2/3and 73.8 dB·Hz^2/3third-order intermodulation distortion (IMD3) spurious free dynamic range (SFDR) at 1 MHz and 10 MHz respectively. We demonstrate two control applications, laser stabilization in a Pound-Drever Hall (PDH) lock loop, reducing laser frequency noise by 40 dB, and as a laser carrier tracking filter. This PZT modulator design can be extended to the visible in the ultra-low loss silicon nitride platform with minor waveguide design changes. This integration of PZT modulation in the ultra-low loss silicon nitride waveguide platform enables modulator control functions in a wide range of visible to IR applications such as atomic and molecular transition locking for cooling, trapping and probing, controllable optical frequency combs, low-power external cavity tunable lasers, quantum computers, sensors and communications, atomic clocks, and tunable ultra-low linewidth lasers and ultra-low phase noise microwave synthesizers.

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