A 16nm 25mm 2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators
- Award ID(s):
- 1718160
- PAR ID:
- 10119013
- Date Published:
- Journal Name:
- 2019 Symposium on VLSI Circuits
- Page Range / eLocation ID:
- C34 to C35
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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