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   Mortensen, Abigail; Pomerville, Scott; Whalley, David; Onder, Soner; Uh, Gang-Ryung (June 2023, Languages, Compilers, and Tools for Embedded Systems)

   Implementation of a new instruction set architecture (ISA) is a non-trivial task which involves significant modifications to the system software, such as the compiler, the assembler, and the linker. This task also includes modifying and verifying functional and cycle accurate simulators to facilitate correct simulation and performance evaluation of programs under the new ISA. Isolating errors in these software components becomes extremely challenging and demands automated and semi-automated mechanisms since neither the compilation infrastructure nor the simulation infrastructure can be trusted as both parties have been heavily modified. Bootstrapping a new ISA is very common in embedded systems since there is a greater variety of embedded ISAs due to often not having a need to support backward compatibility of executables. In this paper, we present the tools and the verification mechanisms we have implemented to support the development of a number of related, but distinct ISAs. These ISAs are similar in complexity to the RISC-V ISA, and range from simple pipelined and superscalar processor ISAs, to a complete VLIW ISA. Our work in developing the system software and simulators for these ISAs demonstrate that a step-by-step semi-automated approach which relies on simple invariants can facilitate effective bootstrapping of the complete system software and the simulator infrastructure. 

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2. Property-driven Automatic Generation of Reduced-ISA Hardware

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   Bleier, Nathan; Sartori, John; Kumar, Rakesh (December 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC))
3. Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures

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   Prodromou, Andreas; Venkat, Ashish; Tullsen, Dean M. (January 2019, Proceedings of the 10th International Workshop on Programming Models and Applications for Multicores and Manycores)
4. BasicBlocker: ISA Redesign to Make Spectre-Immune CPUs Faster

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5. Execution Dependence Extension (EDE): ISA Support for Eliminating Fences

   https://doi.org/10.1109/ISCA52012.2021.00043  

   Shull, Thomas; Vougioukas, Ilias; Nikoleris, Nikos; Elsasser, Wendy; Torrellas, Josep (June 2021, International Symposium on Computer Architecture (ISCA))