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1. A Novel Polymorphic Gate Based Circuit Fingerprinting Technique

   Wang, T.; Cui, X.; Yu, D.; Aramoon, O.; Dunlap, T.; Qu, G.; Cui, X. (May 2018, Proceedings - Great Lakes Symposium on VLSI)

   Polymorphic gates are reconfigurable devices that deliver multiple functionalities at different temperature, supply voltage or external inputs. Capable of working in different modes, polymorphic gate is a promising candidate for embedding secret information such as fingerprints. In this paper, we report five polymorphic gates whose functionality varies in response to specific control input and propose a circuit fingerprinting scheme based on these gates. The scheme selectively replaces standard logic cells by polymorphic gates whose functionality differs with the standard cells only on Satisfiability Don’t Care conditions. Additional dummy fingerprint bits are also introduced to enhance the fingerprint’s robustness against attacks such as fingerprint removal and modification. Experimental results on ISCAS and MCNC benchmark circuits demonstrate that our scheme introduces low overhead. More specifically, the average overhead in area, speed and power are 4.04%, 6.97% and 4.15% respectively when we embed 64-bit fingerprint that consists of 32 real fingerprint bits and 32 dummy bits. This is only half of the overhead of the other known approach when they create 32-bit fingerprints. 

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2. An explicitly magnetic modified embedded atom method formalism for coupled spin dynamics and molecular dynamics

   https://doi.org/10.1088/1361-651X/ad90f9  

   Dickel, D; Baskes, M I (November 2024, Modelling and Simulation in Materials Science and Engineering)

   Abstract In this paper, we augment the modified embedded atom method formalism to include magnetic spin–spin interactions for elements with a persistent magnetic moment. While previous spin coupling methods have been based on pair potentials, our Magnetic MEAM formalism, which we term MagMEAM, incorporates the many-body and angular effects of MEAM allowing for the strength of the magnetic interaction to vary with atomic environment. In particular, this allows potentials using this formalism to differentiate the magnetic interaction of different stable phases of magnetic elements such as the ferritic and austenitic phases of iron. This, in turn, allows for a more robust and realistic description of magnetism in polymorphic materials than was previously possible. The motivation for MagMEAM, including the insufficiency of magnetic pair potentials, is presented and the structure of the formalism is developed. A sample iron potential is developed using this formalism and shown to exceed the capabilities of existing magnetic pair potentials by simultaneously reproducing the magnetic energy of both martensite and austenite as well as the dynamic mechanical and magnetic properties of martensite. This newly designed formalism will allow for deeper explorations in the the complex interaction between different phases of polymorphic magnetic materials at the molecular dynamics scale. 

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3. Polymorphic Circuit Generation Using Random Boolean Logic Expansion

   https://doi.org/10.1145/3341105.3374031  

   McDonald, J.; Stroud, T.; and Andel, T. (March 2020, 35th ACM/SIGAPP Symposium On Applied Computing)

   Securing applications on untrusted platforms can involve protection against legitimate end-users who act in the role of malicious reverse engineers and hackers. Such adversaries have access to the full execution environment of programs, whether the program comes in the form of software or hardware. In this paper, we consider the nature of obfuscating algorithms that perform iterative, step-wise transformation of programs into more complex forms that are intended to increase the complexity (time, resources) for malicious reverse engineers. We consider simple Boolean logic programs as the domain of interest and examine a specific transformation technique known as iterative sub-circuit selection and replacement (ISR), which represents a practical, syntactic approach for obfuscation. Specifically, we focus on improving the security of ISR by maximizing the flexibility and potential security of the replacement step of the algorithm which can be formulated in the following question: given a selection of Boolean logic gates (i.e., a sub-circuit), how can we produce a semantically equivalent (polymorphic) version of the sub-circuit such that the distribution of potential replacements represents a random, uniform distribution from the set of all possible replacements. This practical question is related to the theoretic study of indistinguishability obfuscation, where a transformer for a class of circuits guarantees that given any two semantically equivalent circuits from the class, the distribution of variants from their obfuscation are computationally indistinguishable. Ideally, polymorphic circuits that follow a random, uniform distribution provide stronger protection against malicious analyzers that target identification of distinct patterns as a basis for deobfuscation and simplification. In this paper, we introduce a novel approach for polymorphic circuit replacement called random Boolean logic expansion (RBLE), which applies Boolean logic laws (of reduction) in reverse. We compare this approach against another proposed method of polymorphic replacement that relies on static circuit libraries. As a contribution, we show the strengths and weaknesses of each approach, examine initial results from empirical studies to estimate the uniformity of polymorphic distributions, and provide the argument for how such algorithms can be readily applied in software contexts. RBLE provides a unique method to generate polymorphic variants of arbitrary input, output, and gate size. We report initial findings for studying variants produced by this method and, from empirical evaluation, show that RBLE has promise for generating distributions of unique, uniform circuits when size is unconstrained, but for targeted size distributions, the approach requires some adjustment in order to reach potential circuit variants. 

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4. Non-reciprocal parity-time symmetry breaking based on magneto-optical and gain/loss double ring resonators

   https://doi.org/10.1364/OME.450821  

   Kawaguchi, Yuma; Alù, Andrea; Khanikaev, Alexander_B (March 2022, Optical Materials Express)

   In this paper, we explore the operation of a nonreciprocal non-Hermitian system consisting of a lossy magneto-optical ring resonator coupled to another ring resonator with gain and loss, and we demonstrate that such a system can exhibit non-reciprocity-based broken parity-time (PT) symmetry and supports one-way exceptional points. The nonreciprocal PT-phase transition is analyzed with the use of both analytical tools based on coupled-mode theory and two-dimensional finite element method simulations. Our calculations show that the response of the system strongly depends on the regime of operation – broken or preserved PT-symmetry. This response is leveraged to show that the system can operate as an optical isolator or a one-way laser with functionality tuned by adjusting loss/gain in the second ring resonator. The proposed system can thus be promising for device applications such as magnetically or even optically switchable non-reciprocal devices and one-way micro-ring lasers. 

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5. Protection Against Physical Attacks Through Self-Destructive Polymorphic Latch

   Cannon, A.; Farheen, T.; Roy, S; Tajik, S.; Forte, D. (November 2023, International Conference on Computer-Aided Design (ICCAD))

   On-chip assets, such as cryptographic keys, intermediate cipher computations, obfuscation keys, and hardware security primitive outputs, are usually stored in volatile memories, e.g., registers and SRAMs. Such volatile memories could be read out using active physical attacks, such laser-assisted side-channels. One way to protect assets stored in volatile memories can be the employment of sensors that detect active physical attacks and trigger complete zeroization of sensitive data. However, hundreds or thousands of clock cycles are often needed to accomplish this. Further, the sensing and self-destruction mechanisms are decoupled from the sensitive circuitry and can be disabled separately by an adversary. Moreover, defensive actions (e.g., zeroization) may be disabled by bringing the CPU/SoC into an inoperable condition, while registers may still hold their data, making them susceptible. This paper proposes a self-destructive latch to protect sensitive data from active side-channel attacks, which require supply voltage manipulations.Our proposed latch senses supply voltage interference required during such attacks, and reacts instantaneously by entering a forbidden data state, erasing its stored data. The design uses a NULL convention logic (NCL)- based polymorphic NOR/NAND gate, which changes its functionality with supply voltage. Our results show that the latch is stable across temperature and process variation reacting to attacks with 91% confidence. Even for the 9% where data is not destroyed, in 3.33% of cases data flips its state which makes reliable extraction difficult for an attacker. The polymorphic latch is straightforward to implement due to its NCL implementation and the voltage for the self-destructive behavior is easily altered by resizing only two transistors. Further, this self-destructive behavior extends to registers which are built out of latches. 

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