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1. Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

   https://doi.org/10.1145/3524068  

   Song, Shihao; Balaji, Adarsha; Das, Anup; Kandasamy, Nagarajan (March 2022, ACM Transactions on Embedded Computing Systems)

   An emerging use-case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of a machine learning inference task, making these platforms an attractive solution for embedded ML systems. We present a design-technology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a Non-Volatile Memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality-of-service (QoS) of an embedded ML system. At a finer granularity, the latency inside a PE depends on 1) the delay introduced by parasitic components on its current paths, and 2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing a machine-learning inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of machine-learning inference tasks without incurring high cost-per-bit. 

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2. Expressive Quantum Perceptrons for Quantum Neuromorphic Computing

   https://doi.org/10.1088/2058-9565/ad9fa4  

   Araiza_Bravo, Oscar_Rodrigo; Patti, Taylor_L; Najafi, Khadijeh; Gao, Xun; Yelin, Susanne_F (December 2024, Quantum Science and Technology)

   Abstract Quantum neuromorphic computing (QNC) is a sub-field of quantum machine learning (QML) that capitalizes on inherent system dynamics. As a result, QNC can run on contemporary, noisy quantum hardware and is poised to realize challenging algorithms in the near term. One key issue in QNC is the characterization of the requisite dynamics for ensuring expressive quantum neuromorphic computation. We address this issue by proposing a building block for QNC architectures, what we call quantum perceptrons (QPs). Our proposed QPs compute based on the analog dynamics of interacting qubits with tunable coupling constants. We show that QPs are, with restricted resources, a quantum equivalent to the classical perceptron, a simple mathematical model for a neuron that is the building block of various machine learning architectures. \framing{Moreover, we show that QPs are theoretically capable of producing any unitary operation.} Thus, QPs are computationally more expressive than their classical counterparts. As a result, QNC architectures built our of QPs are, theoretically, universal. We introduce a technique for mitigating barren plateaus in QPs called entanglement thinning. We demonstrate QPs' effectiveness by applying them to numerous QML problems, including calculating the inner products between quantum states, entanglement witnessing, and quantum metrology. Finally, we discuss potential implementations of QPs and how they can be used to build more complex QNC architectures. 

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3. Floating-Point Formats and Arithmetic for Highly Accurate Multi-Layer Perceptrons

   https://doi.org/10.1109/NANO58406.2023.10231201  

   Niknia, Farzad; Wang, Ziheng; Liu, Shanshan; Reviriego, Pedro; Louri, Ahmed; Lombardi, Fabrizio (July 2023, IEEE)

   The data precision can significantly affect the accuracy and overhead metrics of hardware accelerators for different applications such as artificial neural networks (ANNs). This paper evaluates the inference and training of multi-layer perceptrons (MLPs), in which initially IEEE standard floating-point (FP) precisions (half, single and double) are utilized separately and then compared with mixed-precision FP formats. The mixed-precision calculations are investigated for three critical propagation modules (activation functions, weight updates, and accumulation units). Compared with applying a simple low-precision format, the mixed-precision format prevents an accuracy loss and the occurrence of overflow/underflow in the MLPs while potentially incurring in less hardware overhead in terms of area/power. As the multiply-accumulation is the most dominant operation in trending ANNs, a fully pipelined hardware implementation for the fused multiply-add units is proposed for different IEEE FP formats to achieve a very high operating frequency. 

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4. VLSI hardware architecture for Gaussian process

   C. Deng, Y. Gong (November 2020, Asilomar Conference on Signals, Systems, and Computers)

   null (Ed.)

   Gaussian process (GP) is a popular machine learning technique that is widely used in many application domains, especially in robotics. However, GP is very computation intensive and time consuming during the inference phase, thereby bringing severe challenges for its large-scale deployment in real-time applications. In this paper, we propose two efficient hardware architecture for GP accelerator. One architecture targets for general GP inference, and the other architecture is specifically optimized for the scenario when the data point is gradually observed. Evaluation results show that the proposed hardware accelerator provides significant hardware performance improvement than the general-purpose computing platform. 

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5. CHIRP: C ompact and H igh-Performance FPGA Implementation of Un i fied Hardware Accelerators for R ing-Binary-LWE-based P QC

   https://doi.org/10.1145/3715153  

   Bao, Tianyou; He, Pengzhou; Fujimoto, Daisuke; Hayashi, Yuichi; Xie, Jiafeng (January 2025, ACM Transactions on Reconfigurable Technology and Systems)

   Post-quantum cryptography (PQC) has drawn significant attention from the hardware design research community, especially on field-programmable gate array (FPGA) platforms. In line with this trend, in this paper, we present a novel FPGA-based PQC design work (CHIRP), i.e.,Compact and high-Performance FPGA implementation of unIfied accelerators forRing-Binary-Learning-with-Errors (RBLWE)-basedPQC, a promising lightweight PQC suited for related applications like Internet-of-Things. The proposed accelerators offer flexibility across the available two security levels, thus expanding their application potential. In total, we presented four distinct hardware accelerators tailored to different performance and resource requirements, ranging from resource-constrained devices to high-throughput applications. Our innovation encompasses three key efforts: (i) we derived four optimized algorithms for RBLWE-ENC’s unified operation (covering the available two security levels), allowing flexible switching of security sizes while boosting calculations; (ii) we then presented the four novel accelerators (CHIRP) targeting FPGA platforms, featuring dedicated hardware structures; (iii) we finally conducted a comprehensive evaluation to validate the efficiency of the proposed accelerators on various FPGA devices. Compared to the existing unified design, the proposed accelerator demonstrated up to 91.4% reduction in area-delay product (ADP) on the Straix-V device. Even when compared with the state-of-the-art single security designs, the proposed accelerator (best version) obtains much better resource usage and ADP performance while unified operation (flexibly switching between two security levels) is considered on both AMD-Xilinx and Intel devices. We anticipate the findings of this research will foster advancements in FPGA implementation techniques for lightweight PQC development. 

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