Kolala Venkataramanaiah, Shreyas, Ma, Yufei, Yin, Shihui, Nurvithadhi, Eriko, Dasu, Aravind, Cao, Yu, and Seo, Jae-Sun. Automatic Compiler Based FPGA Accelerator for CNN Training. Retrieved from https://par.nsf.gov/biblio/10138116. International Conference on Field Programmable Logic and Applications (FPL) . Web. doi:10.1109/FPL.2019.00034.

Kolala Venkataramanaiah, Shreyas, Ma, Yufei, Yin, Shihui, Nurvithadhi, Eriko, Dasu, Aravind, Cao, Yu, & Seo, Jae-Sun. Automatic Compiler Based FPGA Accelerator for CNN Training. International Conference on Field Programmable Logic and Applications (FPL), (). Retrieved from https://par.nsf.gov/biblio/10138116. https://doi.org/10.1109/FPL.2019.00034

Kolala Venkataramanaiah, Shreyas, Ma, Yufei, Yin, Shihui, Nurvithadhi, Eriko, Dasu, Aravind, Cao, Yu, and Seo, Jae-Sun. "Automatic Compiler Based FPGA Accelerator for CNN Training". International Conference on Field Programmable Logic and Applications (FPL) (). Country unknown/Code not available. https://doi.org/10.1109/FPL.2019.00034. https://par.nsf.gov/biblio/10138116.

@article{osti_10138116,
place = {Country unknown/Code not available}, title = {Automatic Compiler Based FPGA Accelerator for CNN Training}, url = {https://par.nsf.gov/biblio/10138116}, DOI = {10.1109/FPL.2019.00034}, abstractNote = {}, journal = {International Conference on Field Programmable Logic and Applications (FPL)}, author = {Kolala Venkataramanaiah, Shreyas and Ma, Yufei and Yin, Shihui and Nurvithadhi, Eriko and Dasu, Aravind and Cao, Yu and Seo, Jae-Sun}, }