Kadetotad, Deepak, Berisha, Visar, Chakrabarti, Chaitali, and Seo, Jae-Sun. A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip. Retrieved from https://par.nsf.gov/biblio/10138118. IEEE Solid-State Circuits Letters 2.9 Web. doi:10.1109/LSSC.2019.2936761.

Kadetotad, Deepak, Berisha, Visar, Chakrabarti, Chaitali, & Seo, Jae-Sun. A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip. IEEE Solid-State Circuits Letters, 2 (9). Retrieved from https://par.nsf.gov/biblio/10138118. https://doi.org/10.1109/LSSC.2019.2936761

Kadetotad, Deepak, Berisha, Visar, Chakrabarti, Chaitali, and Seo, Jae-Sun. "A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip". IEEE Solid-State Circuits Letters 2 (9). Country unknown/Code not available. https://doi.org/10.1109/LSSC.2019.2936761. https://par.nsf.gov/biblio/10138118.

@article{osti_10138118,
place = {Country unknown/Code not available}, title = {A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip}, url = {https://par.nsf.gov/biblio/10138118}, DOI = {10.1109/LSSC.2019.2936761}, abstractNote = {}, journal = {IEEE Solid-State Circuits Letters}, volume = {2}, number = {9}, author = {Kadetotad, Deepak and Berisha, Visar and Chakrabarti, Chaitali and Seo, Jae-Sun}, }