An official website of the United States government
Abstract Polymer ferroelectrics are playing an increasingly active role in flexible memory application and wearable electronics. The relaxor ferroelectric dielectric, poly(vinylidene fluoride trifluorethylene (PVDF‐TrFE), although vastly used in organic field‐effect transistors (FETs), has issues with gate leakage current especially when the film thickness is below 500 nm. This work demonstrates a novel method of selective poling the dielectric layer. By using solution‐processed 6,13‐bis(triisopropylsilylethynyl)pentacene (TIPS‐pentacene) as the organic semiconductor, it is shown that textured poling of the PVDF‐TrFE layer dramatically improves FET properties compared to unpoled or uniformly poled ferroelectric films. The texturing is achieved by first vertically poling the PVDF‐TrFE film and then laterally poling the dielectric layer close to the gate electrode. TIPS‐pentacene FETs show on/off ratios of 105and hole mobilities of 1 cm2Vs−1under ambient conditions with operating voltages well below −5 V. The electric field distribution in the dielectric layer is simulated by using finite difference time domain methods.
more »
« less
High- κ polymers of intrinsic microporosity: a new class of high temperature and low loss dielectrics for printed electronics
High performance polymer dielectrics are a key component for printed electronics. In this work, organo-soluble polymers of intrinsic microporosity (PIMs) are reported for the first time to demonstrate desirable dielectric properties with a high permittivity (or κ ), heat resistance, and low dielectric loss simultaneously. Due to the highly dipolar sulfonyl side groups (4.5 D) and rigid contorted polymer backbone, a sulfonylated PIM (SO 2 -PIM) enabled friction-free rotation of sulfonyl dipoles in the nanopores. As such, an optimal balance between relatively high κ and low dielectric loss is achieved in a broad temperature window (−50–200 °C). For example, the discharged energy density reached 17 J cm −3 with κ = 6.0. The discharge efficiency was 94% at 150 °C/300 MV m −1 and 88% at 200 °C/200 MV m −1 . Furthermore, its application as a high- κ gate dielectric in field effect transistors (FETs) is demonstrated. With the bilayer SO 2 -PIM/SiO 2 gate dielectric, InSe FETs exhibited a high electron mobility in the range of 200–400 cm 2 V −1 s −1 , as compared to 40 cm 2 V −1 s −1 for the bare SiO 2 -gated InSe FET. This study indicates that highly dipolar PIMs with a rigid polymer backbone and large free volume are promising as next generation gate dielectric materials for printed electronics.
more »
« less
- Award ID(s):
- 1708990
- PAR ID:
- 10148935
- Date Published:
- Journal Name:
- Materials Horizons
- Volume:
- 7
- Issue:
- 2
- ISSN:
- 2051-6347
- Page Range / eLocation ID:
- 592 to 597
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
More Like this
-
-
Abstract A new class of high‐temperature dipolar polymers based on sulfonylated poly(2,6‐dimethyl‐1,4‐phenylene oxide) (SO2‐PPO) was synthesized by post‐polymer functionalization. Owing to the efficient rotation of highly polar methylsulfonyl side groups below the glass transition temperature (Tg≈220 °C), the dipolar polarization of these SO2‐PPOs was enhanced, and thus the dielectric constant was high. Consequently, the discharge energy density reached up to 22 J cm−3. Owing to its highTg , the SO2‐PPO25sample also exhibited a low dielectric loss. For example, the dissipation factor (tan δ) was 0.003, and the discharge efficiency at 800 MV m−1was 92 %. Therefore, these dipolar glass polymers are promising for high‐temperature, high‐energy‐density, and low‐loss electrical energy storage applications.more » « less
-
We examine if the bundling of semiconducting carbon nanotubes (CNTs) can increase the transconductance and on-state current density of field effect transistors (FETs) made from arrays of aligned, polymer-wrapped CNTs. Arrays with packing density ranging from 20 to 50 bundles μm −1 are created via tangential flow interfacial self-assembly, and the transconductance and saturated on-state current density of FETs with either (i) strong ionic gel gates or (ii) weak 15 nm SiO 2 back gates are measured vs the degree of bundling. Both transconductance and on-state current significantly increase as median bundle height increases from 2 to 4 nm, but only when the strongly coupled ionic gel gate is used. Such devices tested at −0.6 V drain voltage achieve transconductance as high as 50 μS per bundle and 2 mS μm −1 and on-state current as high as 1.7 mA μm −1 . At low drain voltages, the off-current also increases with bundling, but on/off ratios of ∼10 5 are still possible if the largest (95th percentile) bundles in an array are limited to ∼5 nm in size. Radio frequency devices with strong, wraparound dielectric gates may benefit from increased device performance by using moderately bundled as opposed to individualized CNTs in arrays.more » « less
-
Low InP/dielectric interface trap density Dit will enable low subthreshold swings (SS) in mm-wave MOSFETs [1] using InGaAs/InP composite channels [2] for increased breakdown and in tunnel FETs (TFETs) [3] using InAs/InP heterojunctions [4] for increased tunneling probability. Reducing Dit at the etched InP mesa edges of DHBTs and avalanche photodiodes will reduce leakage currents and increase breakdown voltages. While it can be difficult [5] to extract Dit of III-V interfaces from MOSCAP characteristics, Dit can be readily determined from the SS of long gate length Lg MOSFETs. Here we report InP-channel MOSFETs with record low SS indicating record low Dit at the semiconductor-dielectric interface. The devices use a AlOxNy/ZrO2 gate dielectric and a 14nm channel thickness Tch. A sample of 13 MOSFETs at 2 m Lg shows SS=70mV/dec. (mean) ±3 mV/dec. (standard deviation), corresponding to a minimum Dit ~3×1012 cm-2eV-1. The lowest SS observed at 2 m Lg is 66 mV/dec. The results suggest that wide-bandgap InP layers can be incorporated into MOS device designs without large degradations in DC characteristics arising from interface defectsmore » « less
-
Abstract New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of line manufacturing are needed for 3D monolithic integration of thin‐film electronics. Here, three atomic layer deposition (ALD) processes are compared for the fabrication of amorphous zinc tin oxide (ZTO) channels in bottom‐gate, top‐contact n‐channel transistors. As‐deposited ZTO films, made by ALD at 150–200 °C, exhibit semiconducting, enhancement‐mode behavior with electron mobility as high as 13 cm2V−1s−1, due to a low density of oxygen‐related defects. ZTO deposited at 200 °C using a hybrid thermal‐plasma ALD process with an optimal tin composition of 21%, post‐annealed at 400 °C, shows excellent performance with a record high mobility of 22.1 cm2V–1s–1and a subthreshold slope of 0.29 V dec–1. Increasing the deposition temperature and performing post‐deposition anneals at 300–500 °C lead to an increased density of the X‐ray amorphous ZTO film, improving its electrical properties. By optimizing the ZTO active layer thickness and using a high‐kgate insulator (ALD Al2O3), the transistor switching voltage is lowered, enabling electrical compatibility with silicon integrated circuits. This work opens the possibility of monolithic integration of ALD ZTO‐based thin‐film electronics with silicon integrated circuits or onto large‐area flexible substrates.more » « less
- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1039/C9MH01261C
