Abstract In this work, TiO2thin films deposited by the atomic layer deposition (ALD) method were treated with a special N2O plasma surface treatment and used as the gate dielectric for AlGaN/GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs). The N2O plasma surface treatment effectively reduces defects in the oxide during low-temperature ALD growth. In addition, it allows oxygen atoms to diffuse into the device cap layer to increase the barrier height and thus reduce the gate leakage current. These TiO2films exhibit a dielectric constant of 54.8 and a two-terminal current of 1.96 × 10−10A mm−1in 2μm distance. When applied as the gate dielectric, the AlGaN/GaN MISHEMT with a 2μm-gate-length shows a high on/off ratio of 2.59 × 108and a low subthreshold slope (SS) of 84 mV dec−1among all GaN MISHEMTs using TiO2as the gate dielectric. This work provides a feasible way to significantly improve the TiO2film electrical property for gate dielectrics, and it suggests that the developed TiO2dielectric is a promising high-κgate oxide and a potential passivation layer for GaN-based MISHEMTs, which can be further extended to other transistors.
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InP MOSFETs Exhibiting Record 70 mV/dec Subthreshold Swing
Low InP/dielectric interface trap density Dit will enable low subthreshold swings (SS) in mm-wave MOSFETs [1] using InGaAs/InP composite channels [2] for increased breakdown and in tunnel FETs (TFETs) [3] using InAs/InP heterojunctions [4] for increased tunneling probability. Reducing Dit at the etched InP mesa edges of DHBTs and avalanche photodiodes will reduce leakage currents and increase breakdown voltages. While it can be difficult [5] to extract Dit of III-V interfaces from MOSCAP characteristics, Dit can be readily determined from the SS of long gate length Lg MOSFETs. Here we report InP-channel MOSFETs with record low SS indicating record low Dit at the semiconductor-dielectric interface. The devices use a AlOxNy/ZrO2 gate dielectric and a 14nm channel thickness Tch. A sample of 13 MOSFETs at 2 m Lg shows SS=70mV/dec. (mean) ±3 mV/dec. (standard deviation), corresponding to a minimum Dit ~3×1012 cm-2eV-1. The lowest SS observed at 2 m Lg is 66 mV/dec. The results suggest that wide-bandgap InP layers can be incorporated into MOS device designs without large degradations in DC characteristics arising from interface defects
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- Award ID(s):
- 1640030
- PAR ID:
- 10114597
- Date Published:
- Journal Name:
- 2019 IEEE Device Research Conference
- Volume:
- NA
- Issue:
- NS
- Page Range / eLocation ID:
- nA
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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