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1. Interconnect-Aware Tests to Complement Gate-Exhaustive Tests

   Pomeranz, I ; Venkataraman, S ( May 2018 , European Test Symposium)

   Gate-exhaustive and cell-aware tests are generated based on input patterns of cells in a design. While the tests provide thorough testing of the cells, the interconnects between them are tested only as input and output lines of cells. This paper defines cell-based faults that allow the interconnects to be tested more thoroughly within a uniform framework that only targets input patterns of cells. In contrast to a real cell that is part of the design, a dummy cell is used for defining interconnect-aware faults. Using a gate-level description of the circuit, a dummy cell contains an interconnect, an output gate of the real cell that drives it, and an input gate of the real cell that it drives. Experimental results for benchmark circuits show that many of the interconnect-aware faults are not detected accidentally by gate-exhaustive tests, and that the quality of the test set is improved by targeting interconnect-aware faults. Here, quality is measured by the numbers of detections of single stuck-at faults in a gate-level representation of the circuit. 

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2. Digital logic for soft devices

   https://doi.org/10.1073/pnas.1820672116  

   Preston, Daniel J. ; Rothemund, Philipp ; Jiang, Haihui Joy ; Nemitz, Markus P. ; Rawson, Jeff ; Suo, Zhigang ; Whitesides, George M. ( March 2019 , Proceedings of the National Academy of Sciences)

   Although soft devices (grippers, actuators, and elementary robots) are rapidly becoming an integral part of the broad field of robotics, autonomy for completely soft devices has only begun to be developed. Adaptation of conventional systems of control to soft devices requires hard valves and electronic controls. This paper describes completely soft pneumatic digital logic gates having a physical scale appropriate for use with current (macroscopic) soft actuators. Each digital logic gate utilizes a single bistable valve—the pneumatic equivalent of a Schmitt trigger—which relies on the snap-through instability of a hemispherical membrane to kink internal tubes and operates with binary high/low input and output pressures. Soft, pneumatic NOT, AND, and OR digital logic gates—which generate known pneumatic outputs as a function of one, or multiple, pneumatic inputs—allow fabrication of digital logic circuits for a set–reset latch, two-bit shift register, leading-edge detector, digital-to-analog converter (DAC), and toggle switch. The DAC and toggle switch, in turn, can control and power a soft actuator (demonstrated using a pneu-net gripper). These macroscale soft digital logic gates are scalable to high volumes of airflow, do not consume power at steady state, and can be reconfigured to achieve multiple functionalities from a single design (including configurations that receive inputs from the environment and from human users). This work represents a step toward a strategy to develop autonomous control—one not involving an electronic interface or hard components—for soft devices.

    

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3. HSC-FPGA: A Hybrid Spin/Charge FPGA Leveraging the Cooperating Strengths of CMOS and MTJ Devices

   Zand, Ramtin ; DeMara, Ronald F. ( February 2019 , Field-programmable gate arrays)

   The HSC-FPGA offers an intriguing feasible architecture for the next generation of configurable fabrics, which allows embracing the advantages of both CMOS and beyond-CMOS technologies without requiring significant modification to the routing structure, programming paradigms, and synthesis tool-chain of the commercial FPGAs. In the HSC-FPGA, the intrinsic characteristics of magnetic random access memory (MRAM)-look-up table (LUT) circuits are used to implement sequential logic, while combinational logic circuits are implemented by static random access memory (SRAM)-LUTs. Fabric-level simulation results for the developed HSC-FPGA show that it can achieve at least 18%, 70%, and 15% reduction in terms of area, standby power, and read power consumption, respectively, for various ISCAS-89 and ITC-99 benchmark circuits compared to conventional SRAM-based FPGAs. The power consumption values can be further decreased by the power-gating allowed by the non-volatility feature of MRAM-LUTs. Moreover, the benefits of increased heterogeneity for reconfigurable computing is extended along realizing probabilistic computing paradigms within a fabric, which is enabled by probabilistic spin logic devices. The cooperating strengths of technology-heterogeneity and heterogeneity in computing paradigm in the proposed HSC-FPGA are leveraged to develop energy-efficient and reliability-aware training and evaluation circuits for deep belief networks with memristive crossbar arrays and p-bit based probabilistic neurons. 

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4. Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift

   https://doi.org/10.1007/s10836-023-06060-z  

   Jiang, Hui ; Zhang, Fanchen ; Dworak, Jennifer ; Nepal, Kundan ; Manikas, Theodore ( April 2023 , Journal of Electronic Testing)

   Test sets that target standard fault models may not always be sufficient for detecting all defects. To evaluate test sets for the detection of unmodeled defects,n-detect test sets (which detect all modeled faults at leastntimes) have previously been proposed. Unfortunately,n-detect test sets are often prohibitively long. In this paper, we investigate the ability of shadow flip-flops connected into a MISR (Multiple Input Signature Register) to detect stuck-at faults fortuitously multiple times during scan shift. We explore which flip-flops should be shadowed to increase the value ofnfor the least detected stuck-at faults for each circuit studied. We then identify which circuit characteristics are most important for determining the cost of the MISR needed to achieve high values ofn. For example, circuits that contain a few flip-flops with upstream fault cones that cover a large percentage of all faults in the circuit can often achieve highn-detect coverage fortuitously with a low-cost MISR. This allows a DFT engineer to predict the viability of this MISR-based approach early in the design cycle.

    

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5. 29.8 SHARC: Self-Healing Analog with RRAM and CNFETs

   https://doi.org/10.1109/ISSCC.2019.8662377  

   Amer, Aya G. ; Ho, Rebecca ; Hills, Gage ; Chandrakasan, Anantha P. ; Shulaker, Max M. ( February 2019 , SHARC: Self-Healing Analog with RRAM and CNFETs)

   Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology for energy-efficient electronics (Fig. 1). Despite this promise, CNTs are subject to substantial inherent imperfections; every ensemble of CNTs includes some percentage of metallic CNTs (m-CNTs). m-CNTs result in conductive shorts between CNFET source and drain, resulting in excessive leakage and degraded (potentially incorrect) circuit functionality (Fig. 1). Several techniques have been developed to remove the majority of m-CNTs (no technique today removes 100% of m-CNTs). While these techniques enabled the first digital CNFET circuits, it is still not possible to realize large-scale CNFET analog or mixed-signal CNFET circuits due to m-CNTs. As shown in Fig. 1, while a digital logic gate can still function correctly in the presence of a small fraction of m-CNTs (but with degraded resilience to noise) [1], a single m-CNT in an analog circuit can result in catastrophic failure (e.g., degrading amplifier gain resulting in functional failure of circuit blocks such as ADCs and DACs)1. This paper presents a circuit design technique, Self-Healing Analog with RRAM and CNFETs (SHARC), that leverages the programmability of non-volatile resistive RAM (RRAM) to automatically “self-heal” analog circuits in the presence of m-CNTs. Using SHARC, we experimentally demonstrate analog CNFET circuits robust to m-CNTs as well as the first mixed-signals CNFET subsystem (4-bit DAC and SAR ADC; these are the largest reported complementary (CMOS) CNFET circuit demonstrations to-date). 

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