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1. A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs

   https://doi.org/10.1145/3174243.3174269  

   Cho, Shenghsun; Patel, Mrunal; Chen, Han; Ferdman, Michael; Milder, Peter (February 2018, FPGA '18 Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays)

   The need for high-performance and low-power acceleration technologies in servers is driving the adoption of PCIe-connected FPGAs in datacenter environments. However, the co-development of the application software, driver, and hardware HDL for server FPGA platforms remains one of the fundamental challenges standing in the way of wide-scale adoption. The FPGA accelerator development process is plagued by a lack of comprehensive full-system simulation tools, unacceptably slow debug iteration times, and limited visibility into the software and hardware at the time of failure. In this work, we develop a framework that pairs a virtual machine and an HDL simulator to enable full-system co-simulation of a server system with a PCIe-connected FPGA. Our framework enables rapid development and debugging of unmodified application software, operating system, device drivers, and hardware design. Once debugged, neither the software nor the hardware requires any changes before being deployed in a production environment. In our case studies, we find that the co-simulation framework greatly improves debug iteration time while providing invaluable visibility into both the software and hardware components. 

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2. LLM4SecHW: Leavering Domain-Specific Large Language Model for Hardware Debugging

   Fu, Weimin; Yang, Kaichen; Dutta, Raj Gautam; Guo, Xiaolong; Qu, Gang (December 2023, Asian Hardware Oriented Security and Trust (AsianHOST))

   This paper presents LLM4SecHW, a novel framework for hardware debugging that leverages domain-specific Large Language Model (LLM). Despite the success of LLMs in automating various software development tasks, their application in the hardware security domain has been limited due to the constraints of commercial LLMs and the scarcity of domain-specific data. To address these challenges, we propose a unique approach to compile a dataset of open-source hardware design defects and their remediation steps, utilizing version control data. This dataset provides a substantial foundation for training machine learning models for hardware. LLM4SecHW employs fine-tuning of medium-sized LLMs based on this dataset, enabling the identification and rectification of bugs in hardware designs. This pioneering approach offers a reference workflow for the application of fine-tuning domain-specific LLMs in other research areas. We evaluate the performance of our proposed system on various open-source hardware designs, demonstrating its efficacy in accurately identifying and correcting defects. Our work brings a new perspective on automating the quality control process in hardware design. 

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3. Cache automaton

   https://doi.org/10.1145/3123939.3123986  

   Subramaniyan, Arun; Wang, Jingcheng; Balasubramanian, Ezhil R.; Blaauw, David; Sylvester, Dennis; Das, Reetuparna (October 2017, MICRO-50 '17 Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture)

   Finite State Automata are widely used to accelerate pattern matching in many emerging application domains like DNA sequencing and XML parsing. Conventional CPUs and compute-centric accelerators are bottlenecked by memory bandwidth and irregular memory access patterns in automata processing. We present Cache Automaton, which repurposes last-level cache for automata processing, and a compiler that automates the process of mapping large real world Non-Deterministic Finite Automata (NFAs) to the proposed architecture. Cache Automaton extends a conventional last-level cache architecture with components to accelerate two phases in NFA processing: state-match and state-transition. State-matching is made efficient using a sense-amplifier cycling technique that exploits spatial locality in symbol matches. State-transition is made efficient using a new compact switch architecture. By overlapping these two phases for adjacent symbols we realize an efficient pipelined design. We evaluate two designs, one optimized for performance and the other optimized for space, across a set of 20 diverse benchmarks. The performance optimized design provides a speedup of 15× over DRAM-based Micron's Automata Processor and 3840× speedup over processing in a conventional x86 CPU. The proposed design utilizes on an average 1.2MB of cache space across benchmarks, while consuming 2.3nJ of energy per input symbol. Our space optimized design can reduce the cache utilization to 0.72MB, while still providing a speedup of 9× over AP. 

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4. Predictive Scheduling for Virtual Reality

   https://doi.org/10.1109/INFOCOM41043.2020.9155249  

   Hou, I-Hong; Naghsh, Narges Zarnaghi; Paul, Sibendu; Hu, Y. Charlie; Eryilmaz, Atilla (July 2020, IEEE Infocom 2020)

   null (Ed.)

   A significant challenge for future virtual reality (VR) applications is to deliver high quality-of-experience, both in terms of video quality and responsiveness, over wireless networks with limited bandwidth. This paper proposes to address this challenge by leveraging the predictability of user movements in the virtual world. We consider a wireless system where an access point (AP) serves multiple VR users. We show that the VR application process consists of two distinctive phases, whereby during the first (proactive scheduling) phase the controller has uncertain predictions of the demand that will arrive at the second (deadline scheduling) phase. We then develop a predictive scheduling policy for the AP that jointly optimizes the scheduling decisions in both phases. In addition to our theoretical study, we demonstrate the usefulness of our policy by building a prototype system. We show that our policy can be implemented under Furion, a Unity-based VR gaming software, with minor modifications. Experimental results clearly show visible difference between our policy and the default one. We also conduct extensive simulation studies, which show that our policy not only outperforms others, but also maintains excellent performance even when the prediction of future user movements is not accurate. 

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5. Computational toolkits for model-based design and optimization

   https://doi.org/10.1016/j.coche.2023.100994  

   Agi, Damian T; Jones, Kyla D; Watson, Madelynn J; Lynch, Hailey G; Dougher, Molly; Chen, Xinhe; Carlozo, Montana N; Dowling, Alexander W (March 2024, Current Opinion in Chemical Engineering)

   Sundmacher, K. (Ed.)

   We review recent advances in software platforms for model-based design (MBD) organized in five overarching themes — from (1) simulation to optimization, (2) commercial to open-source, (3) process-centric to multiscale, (4) mechanistic to data-driven, and (5) deterministic to uncertain — illustrated with several recent examples in membrane system design. We posit MBD provides (chemical) engineers with principled frameworks to tackle global grand challenges such as sustainable energy, clean water, and equitable access to healthcare by integrating knowledge across disciplines. As such, we predict MBD software, which has historically focused on engineered systems, will evolve to interact with models for natural and social systems more holistically. Finally, we emphasize the importance of open-source software development, especially by users who become contributors. 

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