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1. The Colored Refresh Server for DRAM

   https://doi.org/10.1109/ISORC.2019.00015  

   Pan, Xing; Mueller, Frank (May 2019, IEEE International Symposium on Real-Time Computing (ISORC))

   Bounding each task’s worst-case execution time (WCET) accurately is essential for real-time systems to determine if all deadlines can be met. Yet, access latencies to Dynamic Random Access Memory (DRAM) vary significantly due to DRAM refresh, which blocks access to memory cells. Variations further increase as DRAM density grows. This work contributes the “Colored Refresh Server” (CRS), a uniprocessor scheduling paradigm that partitions DRAM in two distinctly colored groups such that refreshes of one color occur in parallel to the execution of real-time tasks of the other color. By executing tasks in phase with periodic DRAM refreshes with opposing colors, memory requests no longer suffer from refresh interference. Experimental results confirm that refresh overhead 

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2. Work in Progress: Reducing WCET Estimation by Increasing the Number of Persistent Blocks

   https://doi.org/10.1109/RTAS65571.2025.00011  

   Geller, Breanna; Rainey, Kyle; Tessler, Corey; Modekurthy, Prashant (May 2025, IEEE)

   Safety-critical systems depend on the temporal guarantees provided by schedulability analysis of hard real-time systems. Worst-case execution time analysis (WCET) is a necessary component in schedulability analysis of hard real-time systems. A central goal of WCET analysis is to produce a tight bound, since tighter bounds (generally) increase the schedulability of a system. Cache memory is an impediment to tight WCET analysis due to the variability it introduces into task systems. However, static modification of memory access patterns within mutable objects may increase cache-hits and reduce WCET. Herein, a mechanism for modifying and analyzing hard real-time tasks is proposed. The proposed mechanism leverages existing persistence analysis to identify sets of blocks to retain in cache during execution. Retention guarantees persistence, resulting in tighter WCET analysis. 

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3. RT-Gang: Real-Time Gang Scheduling Framework for Safety-Critical Systems

   Ali, Waqar; Yun, Heechul. (January 2019, Proceedings - IEEE Real-Time and Embedded Technology and Applications Symposium)

   In this paper, we present RT-Gang: a novel realtime gang scheduling framework that enforces a one-gang-at-atime policy. We find that, in a multicore platform, co-scheduling multiple parallel real-time tasks would require highly pessimistic worst-case execution time (WCET) and schedulability analysis—even when there are enough cores—due to contention in shared hardware resources such as cache and DRAM controller. In RT-Gang, all threads of a parallel real-time task form a real-time gang and the scheduler globally enforces the one-gangat-a-time scheduling policy to guarantee tight and accurate task WCET. To minimize under-utilization, we integrate a state-of-the-art memory bandwidth throttling framework to allow safe execution of best-effort tasks. Specifically, any idle cores, if exist, are used to schedule best-effort tasks but their maximum memory bandwidth usages are strictly throttled to tightly bound interference to real-time gang tasks. We implement RT-Gang in the Linux kernel and evaluate it on two representative embedded multicore platforms using both synthetic and real-world DNN workloads. The results show that RT-Gang dramatically improves system predictability and the overhead is negligible. 

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4. Deterministic Memory Abstraction and Supporting Multicore System Architecture

   https://doi.org/10.4230/LIPIcs.ECRTS.2018.1  

   Farshchi, Farzad; Valsan, Prathap Kumar; Mancuso, Renato; Yun, Heechul (January 2018, Leibniz international proceedings in informatics)

   Poor time predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform-the OS and hardware-guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache, and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach. 

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5. Demand Characterization of CPS with Conditionally-Enabled Sensors

   https://doi.org/10.1109/RTCSA52859.2021.00025  

   Willcock, Aaron; Fisher, Nathan; Chantem, Thidapat (August 2021, International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA))

   Characterizing computational demand of Cyber-Physical Systems (CPS) is critical for guaranteeing that multiple hard real-time tasks may be scheduled on shared resources without missing deadlines. In a CPS involving repetition such as industrial automation systems found in chemical process control or robotic manufacturing, sensors and actuators used as part of the industrial process may be conditionally enabled (and disabled) as a sequence of repeated steps is executed. In robotic manufacturing, for example, these steps may be the movement of a robotic arm through some trajectories followed by activation of end-effector sensors and actuators at the end of each completed motion. The conditional enabling of sensors and actuators produces a sequence of Monotonically Ascending Execution times (MAE) with lower WCET when the sensors are disabled and higher WCET when enabled. Since these systems may have several predefined steps to follow before repeating the entire sequence each unique step may result in several consecutive sequences of MAE. The repetition of these unique sequences of MAE result in a repeating WCET sequence. In the absence of an efficient demand characterization technique for repeating WCET sequences composed of subsequences with monotonically increasing execution time, this work proposes a new task model to describe the behavior of real-world systems which generate large repeating WCET sequences with subsequences of monotonically increasing execution times. In comparison to the most applicable current model, the Generalized Multiframe model (GMF), an empirically and theoretically faster method for characterizing the demand is provided. The demand characterization algorithm is evaluated through a case study of a robotic arm and simulation of 10,000 randomly generated tasks where, on average, the proposed approach is 231 and 179 times faster than the state-of-the-art in the case study and simulation respectively. 

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