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1. Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning

   https://doi.org/10.23919/DATE48585.2020.9116330  

   Liu, Mingjie; Zhu, Keren; Gu, Jiaqi; Shen, Linxiao; Tang, Xiyuan; Sun, Nan; Pan, David Z. (March 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE))

   Despite tremendous efforts in analog layout automation, little adoption has been demonstrated in practical design flows. Traditional analog layout synthesis tools use various heuristic constraints to prune the design space to ensure post layout performance. However, these approaches provide limited guarantee and poor generalizability due to a lack of model mapping layout properties to circuit performance. In this paper, we attempt to shorten the gap in post layout performance modeling for analog circuits with a quantitative statistical approach. We leverage a state-of-the-art automatic analog layout tool and industry-level simulator to generate labeled training data in an automated manner. We propose a 3D convolutional neural network (CNN) model to predict the relative placement quality using well-crafted placement features. To achieve data-efficiency for practical usage, we further propose a transfer learning scheme that greatly reduces the amount of data needed. Our model would enable early pruning and efficient design explorations for practical layout design flows. Experimental results demonstrate the effectiveness and generalizability of our method across different operational transconductance amplifier (OTA) designs. 

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2. GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance

   https://doi.org/10.1109/ICCAD45719.2019.8942164  

   Zhu, Keren; Liu, Mingjie; Lin, Yibo; Xu, Biying; Li, Shaolan; Tang, Xiyuan; Sun, Nan; Pan, David Z. (November 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD))

   Due to sensitive layout-dependent effects and varied performance metrics, analog routing automation for performance-driven layout synthesis is difficult to generalize. Existing research has proposed a number of heuristic layout constraints targeting specific performance metrics. However, previous frameworks fail to automatically combine routing with human intelligence. This paper proposes a novel, fully automated, analog routing paradigm that leverages machine learning to provide routing guidance, mimicking the sophisticated manual layout approaches. Experiments show that the proposed methodology obtains significant improvements over existing techniques and achieves competitive performance to manual layouts while being capable of generalizing to circuits of different functionality. 

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3. Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing

   https://doi.org/10.3390/jlpea13040058  

   Ige, Afolabi; Yang, Linhao; Yang, Hang; Hasler, Jennifer; Hao, Cong (December 2023, Journal of Low Power Electronics and Applications)

   The design of analog computing systems requires significant human resources and domain expertise due to the lack of automation tools to enable these highly energy-efficient, high-performance computing nodes. This work presents the first automated tool flow from a high-level representation to a reconfigurable physical device. This tool begins with a high-level algorithmic description, utilizing either our custom Python framework or the XCOS GUI, to compile and optimize computations for integration into an Integrated Circuit (IC) design or a Field Programmable Analog Array (FPAA). An energy-efficient embedded speech classifier benchmark illustrates the tool demonstration, automatically generating GDSII layout or FPAA switch list targeting. 

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4. Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction

   https://doi.org/10.1145/3566097.3567881  

   Chang, Chen-Chia; Pan, Jingyu; Xie, Zhiyao; Li, Yaguang; Lin, Yishuang; Hu, Jiang; Chen, Yiran (January 2023, The 28th Asia and South Pacific Design Automation Conference)

   Analog integrated circuit (IC) placement is a heavily manual and time-consuming task that has a significant impact on chip quality. Several recent studies apply machine learning (ML) techniques to directly predict the impact of placement on circuit performance or even guide the placement process. However, the significant diversity in analog design topologies can lead to different impacts on performance metrics (e.g., common-mode rejection ratio (CMRR) or offset voltage). Thus, it is unlikely that the same ML model structure will achieve the best performance for all designs and metrics. In addition, customizing ML models for different designs require more tremendous engineering efforts and longer development cycles. In this work, we leverage Neural Architecture Search (NAS) to automatically develop customized neural architectures for different analog circuit designs and metrics. Our proposed NAS methodology supports an unconstrained DAG-based search space containing a wide range of ML operations and topological connections. Our search strategy can efficiently explore this flexible search space and provide every design with the best-customized model to boost the model performance. We make unprejudiced comparisons with the claimed performance of the previous representative work on exactly the same dataset. After fully automated development within only 0.5 days, generated models give 3.61% superior accuracy than the prior art. 

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5. Unified Holistic Memory Management Supporting Multiple Big Data Processing Frameworks over Hybrid Memories

   https://doi.org/10.1145/3511211  

   Chen, Lei; Zhao, Jiacheng; Wang, Chenxi; Cao, Ting; Zigman, John; Volos, Haris; Mutlu, Onur; Lv, Fang; Feng, Xiaobing; Xu, Guoqing Harry; et al (November 2021, ACM Transactions on Computer Systems)

   To process real-world datasets, modern data-parallel systems often require extremely large amounts of memory, which are both costly and energy inefficient. Emerging non-volatile memory (NVM) technologies offer high capacity compared to DRAM and low energy compared to SSDs. Hence, NVMs have the potential to fundamentally change the dichotomy between DRAM and durable storage in Big Data processing. However, most Big Data applications are written in managed languages and executed on top of a managed runtime that already performs various dimensions of memory management. Supporting hybrid physical memories adds a new dimension, creating unique challenges in data replacement. This article proposes Panthera, a semantics-aware, fully automated memory management technique for Big Data processing over hybrid memories. Panthera analyzes user programs on a Big Data system to infer their coarse-grained access patterns, which are then passed to the Panthera runtime for efficient data placement and migration. For Big Data applications, the coarse-grained data division information is accurate enough to guide the GC for data layout, which hardly incurs overhead in data monitoring and moving. We implemented Panthera in OpenJDK and Apache Spark. Based on Big Data applications’ memory access pattern, we also implemented a new profiling-guided optimization strategy, which is transparent to applications. With this optimization, our extensive evaluation demonstrates that Panthera reduces energy by 32–53% at less than 1% time overhead on average. To show Panthera’s applicability, we extend it to QuickCached, a pure Java implementation of Memcached. Our evaluation results show that Panthera reduces energy by 28.7% at 5.2% time overhead on average. 

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