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Title: Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach
The data partitioning and scheduling strategies used by DNN accelerators to leverage reuse and perform staging are known as dataflow, which directly impacts the performance and energy efficiency of DNN accelerators. An accelerator micro architecture dictates the dataflow(s) that can be employed to execute layers in a DNN. Selecting a dataflow for a layer can have a large impact on utilization and energy efficiency, but there is a lack of understanding on the choices and consequences of dataflow, and of tools and methodologies to help architects explore the co-optimization design space. In this work, we first introduce a set of data-centric directives to concisely specify the DNN dataflow space in a compiler-friendly form. We then show how these directives can be analyzed to infer various forms of reuse and to exploit them using hardware capabilities. We codify this analysis into an analytical cost model, MAESTRO (Modeling Accelerator Efficiency via Patio-Temporal Reuse and Occupancy), that estimates various cost-benefit tradeoffs of a dataflow including execution time and energy efficiency for a DNN model and hardware configuration. We demonstrate the use of MAESTRO to drive a hardware design space exploration experiment, which searches across 480M designs to identify 2.5M valid designs at an average rate of 0.17M designs per second, including Pareto-optimal throughput- and energy-optimized design points.  more » « less
Award ID(s):
1822919
NSF-PAR ID:
10199644
Author(s) / Creator(s):
; ; ; ; ;
Date Published:
Journal Name:
MICRO '52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture
Page Range / eLocation ID:
754 to 768
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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