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1. Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms

   https://doi.org/10.1109/DCIS.2018.8681492  

   Zhang, Rui ; Yang, Kexin ; Liu, Taizhi ; Milor, Linda ( November 2018 , Design of Circuits and Integrated Systems)

   Advanced FinFET SRAMs undergo reliability degradation due to various front-end and back-end wearout mechanisms. The design of reliable SRAMs benefits from accurate wearout models that are calibrated by accelerated test. With respect to testing, the accelerated conditions which can help separate the dominant wearout mechanisms related to circuit failure is crucial for model calibration and reliability prediction. In this paper, the estimation of optimal accelerated test regions for a 14nm FinFET SRAM under various wearout mechanisms is presented. The dominant regions for specific mechanisms are compared and analyzed for effective testing. It is observed that for our SRAM example circuit only bias temperature instability (BTI) and middle-of-line time-dependent dielectric breakdown (MTDDB) have test regions where their failures can be isolated, while the other mechanisms can’t be extracted individually due to acceptable regions’ overlap. Meanwhile, the SRAM cell activity distribution has a small influence on test regions and selectivity. 

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2. Impact of front-end wearout mechanisms on FinFET SRAM soft error rate

   https://doi.org/10.1016/j.microrel.2019.113487  

   Zhang, R. ; Liu, Z. ; Yang, K. ; Liu, T. ; Cai, W. ; Milor, L. ( September 2019 , Microelectronics reliability)

   null (Ed.)

   We build a modelling and simulation flow to study how the front-end wearout mechanisms affect the FinFET SRAM soft error rate. This flow incorporates process variation, such as device dimensions, and degradation parameters. We first checked the impact of process parameters on critical charge and soft error rate. It is found that a larger gate length and higher temperature help us obtain better reliability for a FinFET SRAM cell under radiation, with a higher Qcrit and lower SER. Then, the time-dependent shift of Qcrit and SER is displayed. Within its range between 0% and 50%, a lower duty ratio leads to worse reliability due to soft errors. Moreover, a higher transition rate causes worse reliability. 

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3. Inverse Design of FinFET SRAM Cells

   https://doi.org/10.1109/IRPS45951.2020.9129530  

   Zhang, Rui ; Liu, Zhaocheng ; Yang, Kexin ; Liu, Taizhi ; Cai, Wenshan ; Milor, Linda ( April 2020 , IEEE International Reliability Physics Symposium)

   null (Ed.)

   A convenient method based on deep neural networks and an evolutionary algorithm is proposed for the inverse design of FinFET SRAM cells. Inverse design helps designers who have less device physics knowledge obtain cell configurations that provide the desired performance metrics under selected wearout conditions, such as a set specific stress time and use scenario that creates a specific activity level (duty cycle and transition rate). The cell configurations being considered consists of various process parameters, such as gate length and fin height, in the presence of variations due to process and wearout. The front-end mechanisms related to wearout include negative bias temperature instability (NBTI), hot carrier injection (HCI), and random telegraph noise (RTN). The process of inverse design is achieved quickly and at good accuracy. 

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4. A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture

   https://doi.org/10.1109/VTS48691.2020.9107583  

   Wang, Wendong ; Guin, Ujjwal ; Singh, Adit ( April 2020 , 2020 IEEE 38th VLSI Test Symposium (VTS))

   null (Ed.)

   The recycling of used integrated circuits (ICs) has raised serious problems in ensuring the integrity of today's globalized semiconductor supply chain. This poses a serious threat to critical infrastructure due to potentially shorter lifetime, lower reliability, and poorer performance from these counterfeit new chips. Recently, we have proposed a highly effective approach for detecting such chips by exploiting the power-up state of on-chip SRAMs. Due to the symmetry of the memory array layout, an equal number of cells power-up to the 0 and 1 logic states in a new unused SRAM; this ratio gets skewed in time due to uneven NBTI aging from normal usage in the field. Although this solution is very effective in detecting recycled ICs, its applicability is somewhat limited as a large number older designs do not have large on-chip memories. In this paper, we propose an alternate approach based on the initial power-up state of scan flip-flops, which are present in virtually every digital circuit. Since the flip-flops, unlike SRAM cells, are generally not perfectly symmetrical in layout, an equal number of scan cells will not power-up to 0 or 1 logic states in most designs. Consequently, a stable time zero reference of 50% logic 0s and 1s cannot be used for determining the subsequent usage of a chip. To overcome this key limitation, we propose a novel solution in this paper that reliably identifies used ICs from testing the part alone, without the need for any additional reference data or even the netlist of the circuit. Through scan testing of the IC, we first identify a significant number of asymmetrically stressed flip-flops in the design, divided into two groups. One group of flip-flops is selected such that it mostly experiences the 1 logic state during functional operation, while the other group mostly experiences the 0 state. The resulting differential stress during operation causes growing disparity over time in the number of 0s (and 1s) observed in these two groups at power-up. When new and unaged, these two groups behave similarly, with similar percentage of 1s (or 0s). However, over time the differential stress makes these counts diverge. We show that this changing count can be a measure of operational aging. Our simulation results show that it is possible to reliably detect used ICs after as little as three months of operation. 

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5. Hot-Trim: Thermal and Reliability Management for Commercial Multi-core Processors Considering Workload Dependent Hot Spots

   https://doi.org/10.1109/TCAD.2022.3216552  

   Zhang, Jinwei ; Sadiqbatcha, Sheriff ; Tan, Sheldon X.-D. ( January 2023 , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)

   This work proposes a new dynamic thermal and reliability management framework via task mapping and migration to improve thermal performance and reliability of commercial multi-core processors considering workload-dependent thermal hot spot stress. The new method is motivated by the observation that different workloads activate different spatial power and thermal hot spots within each core of processors. Existing run-time thermal management, which is based on on-chip location-fixed thermal sensor information, can lead to suboptimal management solutions as the temperatures provided by those sensors may not be the true hot spots. The new method, called Hot-Trim, utilizes a machine learning-based approach to characterize the power density hot spots across each core, then a new task mapping/migration scheme is developed based on the hot spot stresses. Compared to existing works, the new approach is the first to optimize VLSI reliabilities by exploring workload-dependent power hot spots. The advantages of the proposed method over the Linux baseline task mapping and the temperature-based mapping method are demonstrated and validated on real commercial chips. Experiments on a real Intel Core i7 quad-core processor executing PARSEC-3.0 and SPLASH-2 benchmarks show that, compared to the existing Linux scheduler, core and hot spot temperature can be lowered by 1.15 to 1.31C. In addition, Hot-Trim can improve the chip's EM, NBTI and HCI related reliability by 30.2%, 7.0% and 31.1% respectively compared to Linux baseline without any performance degradation. Furthermore, it improves EM and HCI related reliability by 29.6% and 19.6% respectively, and at the same time even further reduces the temperature by half a degree compared to the conventional temperature-based mapping technique. 

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