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1. Reliability and accelerated testing of 14nm FinFET ring oscillators

   https://doi.org/10.1109/DCIS201949030.2019.8959834  

   Hsu, S.-H.; Yang, K.; Milor, L. (November 2019, Design of Circuits and Integrated Systems)

   Accelerated lifetime tests are necessary for reliability evaluation of circuits and systems, but the parameters for choosing the test conditions are often unknown. Furthermore, reliability testing is generally performed on test structures that have different properties than actual circuits and systems, which may create inconsistencies in how circuits and systems work in reality. To combat this problem, we use ring oscillators, which are similar to circuits, based on the 14nm FinFET node as the circuit vehicle to extract wearout data. We explore the effects of testing time, sample size, and number of stages on the ability to detect failures for various test conditions, focusing on front-end time dependent dielectric breakdown, which is one of the most dominant wearout mechanisms. 

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2. Impact of front-end wearout mechanisms on FinFET SRAM soft error rate

   https://doi.org/10.1016/j.microrel.2019.113487  

   Zhang, R.; Liu, Z.; Yang, K.; Liu, T.; Cai, W.; Milor, L. (September 2019, Microelectronics reliability)

   null (Ed.)

   We build a modelling and simulation flow to study how the front-end wearout mechanisms affect the FinFET SRAM soft error rate. This flow incorporates process variation, such as device dimensions, and degradation parameters. We first checked the impact of process parameters on critical charge and soft error rate. It is found that a larger gate length and higher temperature help us obtain better reliability for a FinFET SRAM cell under radiation, with a higher Qcrit and lower SER. Then, the time-dependent shift of Qcrit and SER is displayed. Within its range between 0% and 50%, a lower duty ratio leads to worse reliability due to soft errors. Moreover, a higher transition rate causes worse reliability. 

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3. A library based on deep neural networks for modeling the degradation of FinFET SRAM performance metrics due to aging

   https://doi.org/10.1016/j.microrel.2019.113486  

   Zhang, R.; Liu, Z.; Yang, K.; Liu, T.; Cai, W.; MIlor, L. (September 2019, Microelectronics reliability)

   null (Ed.)

   FinFET SRAM cells suffer from front-end wearout mechanisms, such as bias temperature instability and hot carrier injection. In this paper, we built a library based on deep neural networks (DNNs) to speed up the process of simulating FinFET SRAM cells' degradation. This library consists of two parts. The first part calculates circuit configuration parameters, wearout parameters, and the other input variables for the DNN. The second part calls for the DNN to determine the shifted circuit performance metrics. A DNN with more than 99% accuracy is achieved with training data from standard Hspice simulations. The correctness of the DNN is also validated in the presence of input variations. With this library, the simulation speed is one hundred times faster than Hspice simulations. We can display the cell's degradation under various configurations easily and quickly. Also, the DNN-based library can help protect intellectual property without showing users the circuit's details. 

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4. Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology

   https://doi.org/10.1109/DCIS.2018.8681497  

   Yang, Kexin; Zhang, Rui; Liu, Taizhi; Kim, Dae-Hyun; Milor, Linda (November 2018, Design of Circuits and Integrated Systems)

   This paper proposes a methodology to find optimal accelerated test regions for lifetime parameter estimation for not only the traditional reliability concern, frontend-of-line dielectric breakdown (FEOL TDDB), but also the newly emerging wearout mechanism, middle-of-line time dependent dielectric breakdown (MOL TDDB) in 14nm FinFET technology. The framework to find the optimal test regions is introduced; the error estimating methodology is discussed in detail. Three digital circuits are presented for evaluation and comparison. The optimal test regions depend on the circuit size as well as the types of standard cells in the circuits. To ensure accurate lifetime parameter estimation, both error from sampling and error from selectivity should be considered at the same time. As a general guideline, higher estimation accuracy will be achieved by testing gate TDDB lifetime parameters at higher voltages, while testing middle-of-line TDDB at higher temperatures. 

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5. Inverse Design of FinFET SRAM Cells

   https://doi.org/10.1109/IRPS45951.2020.9129530  

   Zhang, Rui; Liu, Zhaocheng; Yang, Kexin; Liu, Taizhi; Cai, Wenshan; Milor, Linda (April 2020, IEEE International Reliability Physics Symposium)

   null (Ed.)

   A convenient method based on deep neural networks and an evolutionary algorithm is proposed for the inverse design of FinFET SRAM cells. Inverse design helps designers who have less device physics knowledge obtain cell configurations that provide the desired performance metrics under selected wearout conditions, such as a set specific stress time and use scenario that creates a specific activity level (duty cycle and transition rate). The cell configurations being considered consists of various process parameters, such as gate length and fin height, in the presence of variations due to process and wearout. The front-end mechanisms related to wearout include negative bias temperature instability (NBTI), hot carrier injection (HCI), and random telegraph noise (RTN). The process of inverse design is achieved quickly and at good accuracy. 

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