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Title: Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms
Advanced FinFET SRAMs undergo reliability degradation due to various front-end and back-end wearout mechanisms. The design of reliable SRAMs benefits from accurate wearout models that are calibrated by accelerated test. With respect to testing, the accelerated conditions which can help separate the dominant wearout mechanisms related to circuit failure is crucial for model calibration and reliability prediction. In this paper, the estimation of optimal accelerated test regions for a 14nm FinFET SRAM under various wearout mechanisms is presented. The dominant regions for specific mechanisms are compared and analyzed for effective testing. It is observed that for our SRAM example circuit only bias temperature instability (BTI) and middle-of-line time-dependent dielectric breakdown (MTDDB) have test regions where their failures can be isolated, while the other mechanisms can’t be extracted individually due to acceptable regions’ overlap. Meanwhile, the SRAM cell activity distribution has a small influence on test regions and selectivity.  more » « less
Award ID(s):
Author(s) / Creator(s):
; ; ;
Date Published:
Journal Name:
Design of Circuits and Integrated Systems
Page Range / eLocation ID:
1 to 6
Medium: X
Sponsoring Org:
National Science Foundation
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