Pamula, Venkata Rajesh, Sun, Xun, Kim, Sung Min, Rahman, Fahim ur, Zhang, Baosen, and Sathe, Visvesh S. A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction. Retrieved from https://par.nsf.gov/biblio/10213689. IEEE Solid-State Circuits Letters 1.12 Web. doi:10.1109/LSSC.2019.2896777.

Pamula, Venkata Rajesh, Sun, Xun, Kim, Sung Min, Rahman, Fahim ur, Zhang, Baosen, & Sathe, Visvesh S. A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction. IEEE Solid-State Circuits Letters, 1 (12). Retrieved from https://par.nsf.gov/biblio/10213689. https://doi.org/10.1109/LSSC.2019.2896777

Pamula, Venkata Rajesh, Sun, Xun, Kim, Sung Min, Rahman, Fahim ur, Zhang, Baosen, and Sathe, Visvesh S. "A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction". IEEE Solid-State Circuits Letters 1 (12). Country unknown/Code not available. https://doi.org/10.1109/LSSC.2019.2896777. https://par.nsf.gov/biblio/10213689.

@article{osti_10213689,
place = {Country unknown/Code not available}, title = {A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction}, url = {https://par.nsf.gov/biblio/10213689}, DOI = {10.1109/LSSC.2019.2896777}, abstractNote = {}, journal = {IEEE Solid-State Circuits Letters}, volume = {1}, number = {12}, author = {Pamula, Venkata Rajesh and Sun, Xun and Kim, Sung Min and Rahman, Fahim ur and Zhang, Baosen and Sathe, Visvesh S.}, editor = {null} }