Venkataramanaiah, Shreyas K., Suh, Han-Sok, Yin, Shihui, Nurvitadhi, Eriko, Dasu, Aravind, Cao, Yu, and Seo, Jae-sun. FPGA-based low-batch training accelerator for modern CNNs featuring high bandwidth memory. Retrieved from https://par.nsf.gov/biblio/10214138. ACM/IEEE International Conference on Computer-Aided Design (ICCAD) . Web. doi:10.1145/3400302.3415643.

Venkataramanaiah, Shreyas K., Suh, Han-Sok, Yin, Shihui, Nurvitadhi, Eriko, Dasu, Aravind, Cao, Yu, & Seo, Jae-sun. FPGA-based low-batch training accelerator for modern CNNs featuring high bandwidth memory. ACM/IEEE International Conference on Computer-Aided Design (ICCAD), (). Retrieved from https://par.nsf.gov/biblio/10214138. https://doi.org/10.1145/3400302.3415643

Venkataramanaiah, Shreyas K., Suh, Han-Sok, Yin, Shihui, Nurvitadhi, Eriko, Dasu, Aravind, Cao, Yu, and Seo, Jae-sun. "FPGA-based low-batch training accelerator for modern CNNs featuring high bandwidth memory". ACM/IEEE International Conference on Computer-Aided Design (ICCAD) (). Country unknown/Code not available. https://doi.org/10.1145/3400302.3415643. https://par.nsf.gov/biblio/10214138.

@article{osti_10214138,
place = {Country unknown/Code not available}, title = {FPGA-based low-batch training accelerator for modern CNNs featuring high bandwidth memory}, url = {https://par.nsf.gov/biblio/10214138}, DOI = {10.1145/3400302.3415643}, abstractNote = {}, journal = {ACM/IEEE International Conference on Computer-Aided Design (ICCAD)}, author = {Venkataramanaiah, Shreyas K. and Suh, Han-Sok and Yin, Shihui and Nurvitadhi, Eriko and Dasu, Aravind and Cao, Yu and Seo, Jae-sun}, editor = {null} }