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1. Inverse Design of FinFET SRAM Cells

   https://doi.org/10.1109/IRPS45951.2020.9129530  

   Zhang, Rui; Liu, Zhaocheng; Yang, Kexin; Liu, Taizhi; Cai, Wenshan; Milor, Linda (April 2020, IEEE International Reliability Physics Symposium)

   null (Ed.)

   A convenient method based on deep neural networks and an evolutionary algorithm is proposed for the inverse design of FinFET SRAM cells. Inverse design helps designers who have less device physics knowledge obtain cell configurations that provide the desired performance metrics under selected wearout conditions, such as a set specific stress time and use scenario that creates a specific activity level (duty cycle and transition rate). The cell configurations being considered consists of various process parameters, such as gate length and fin height, in the presence of variations due to process and wearout. The front-end mechanisms related to wearout include negative bias temperature instability (NBTI), hot carrier injection (HCI), and random telegraph noise (RTN). The process of inverse design is achieved quickly and at good accuracy. 

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2. SRAM Design with OpenRAM in SkyWater 130nm

   https://doi.org/10.1109/ISCAS46773.2023.10181379  

   Cirimelli-Low, Jesse; Khan, Muhammad Hadir; Crow, Samuel; Lonkar, Amogh; Onal, Bugra; Zonenberg, Andrew D.; Guthaus, Matthew R. (May 2023, Proceedings IEEE International Symposium on Circuits and Systems)
3. Identifying Radiation-Induced Micro-SEFIs in SRAM FPGAs

   https://doi.org/10.1109/TNS.2021.3108572  

   Perez-Celis, Andres; Thurlow, Corbin; Wirthlin, Michael (October 2021, IEEE Transactions on Nuclear Science)
4. Phase Transition Material-Assisted Low-Power SRAM Design

   https://doi.org/10.1109/TED.2021.3067849  

   Nibhanupudi, S. S.; Raman, Siddhartha Raman; Kulkarni, Jaydeep P. (May 2021, IEEE Transactions on Electron Devices)

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5. Reconfigurable Real-Time Video Pipelines on SRAM-based FPGAs

   https://doi.org/10.1109/ReConFig48160.2019.8994814  

   Wilson, Andrew E.; Wirthlin, Michael (December 2019, 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig))

   FPGAs are an excellent target for real-time video processing as they provide large amounts of low-level parallelism, low latency, and high bandwidth. However, creating real-time video processing systems on an FPGA is tedious and requires significant effort and low-level digital design skills. This paper presents a technique for creating complex real-time video processing pipelines relatively quickly and easily using partial reconfiguration (PR). A static FPGA system is created that provides a template for a variety of partially reconfigurable video processing cores. A library of video filters has been created that can be inserted into the template regions. At run-time, the user can select the topology of video cores and customize these cores to create complex and unique video pipelines without any understanding of low-level FPGA details. This paper demonstrates this technique with a library of 11 partial reconfigurable regions and 16 video processing cores operating on the Xilinx PYNQ system. 

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