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Title: Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis
Award ID(s):
1704758
NSF-PAR ID:
10271628
Author(s) / Creator(s):
; ; ; ; ; ;
Date Published:
Journal Name:
ACM/IEEE Design Automation Conference (DAC)
Page Range / eLocation ID:
1 to 6
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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