Wang, Zhepeng, Wu, Yawen, Jia, Zhenge, Shi, Yiyu, and Hu, Jingtong. Lightweight Run-Time Working Memory Compression for Deployment of Deep Neural Networks on Resource-Constrained MCUs. Retrieved from https://par.nsf.gov/biblio/10275972. 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) . Web. doi:10.1145/3394885.3439194.

Wang, Zhepeng, Wu, Yawen, Jia, Zhenge, Shi, Yiyu, & Hu, Jingtong. Lightweight Run-Time Working Memory Compression for Deployment of Deep Neural Networks on Resource-Constrained MCUs. 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), (). Retrieved from https://par.nsf.gov/biblio/10275972. https://doi.org/10.1145/3394885.3439194

Wang, Zhepeng, Wu, Yawen, Jia, Zhenge, Shi, Yiyu, and Hu, Jingtong. "Lightweight Run-Time Working Memory Compression for Deployment of Deep Neural Networks on Resource-Constrained MCUs". 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) (). Country unknown/Code not available. https://doi.org/10.1145/3394885.3439194. https://par.nsf.gov/biblio/10275972.

@article{osti_10275972,
place = {Country unknown/Code not available}, title = {Lightweight Run-Time Working Memory Compression for Deployment of Deep Neural Networks on Resource-Constrained MCUs}, url = {https://par.nsf.gov/biblio/10275972}, DOI = {10.1145/3394885.3439194}, abstractNote = {}, journal = {2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)}, author = {Wang, Zhepeng and Wu, Yawen and Jia, Zhenge and Shi, Yiyu and Hu, Jingtong}, editor = {null} }