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1. Rasco: Resource Allocation and Scheduling Co-design for DAG Applications on Multicore

   https://doi.org/10.1145/3761814  

   Eisenklam, Abigail; Gifford, Robert; Bondar, Georgiy A; Cai, Yifan; Sial, Tushar; Phan, Linh_Thi Xuan; Halder, Abhishek (November 2025, ACM Transactions on Embedded Computing Systems)

   As multicore hardware becomes increasingly prevalent in real-time embedded systems, traditional scheduling techniques that assume a single worst-case execution time for each task are no longer adequate, as they fail to account for the impact of shared resources—such as cache and memory bandwidth—on execution time. When tasks execute concurrently on different cores, their execution times can vary substantially with their allocated resources. Moreover, the instruction rate of a task during a job execution varies with time, and this variation pattern differs across tasks. Therefore, to improve performance it is crucial to incorporate the relationship between the resource budget allocated to each task and its time-varying instruction rate in task modeling, resource allocation, and scheduling algorithm design. Yet, no prior work has considered the fine-grained dynamic resource allocation and scheduling problems jointly while also providing hard real-time guarantees. In this article, we introduce a resource-dependent multi-phase timing model that captures the time-varying instruction rates of a task under different resource allocations and that enables worst-case analysis under dynamic allocation. We present a method for constructing estimates of such a model based on task execution profiles, which can be obtained through measurements. We then presentRasco, a co-design technique for multicore resource allocation and scheduling of real-time DAG applications with end-to-end deadlines.Rascoleverages the resource-dependent multi-phase model of each task to simultaneously allocate resources at a fine granularityandassign task deadlines. This approach maximizes execution progress under resource constraints while providing hard real-time schedulability guarantees. Our evaluation shows thatRascosubstantially enhances schedulability and reduces end-to-end latency compared to the state of the art. 

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2. GCAPS: GPU Context-Aware Preemptive Priority-Based Scheduling for Real-Time Tasks

   https://doi.org/10.4230/LIPIcs.ECRTS.2024.14  

   Wang, Yidi; Liu, Cong; Wong, Daniel; Kim, Hyoseung (January 2024, Schloss Dagstuhl – Leibniz-Zentrum für Informatik)

   Pellizzoni, Rodolfo (Ed.)

   Scheduling real-time tasks that utilize GPUs with analyzable guarantees poses a significant challenge due to the intricate interaction between CPU and GPU resources, as well as the complex GPU hardware and software stack. While much research has been conducted in the real-time research community, several limitations persist, including the absence or limited availability of GPU-level preemption, extended blocking times, and/or the need for extensive modifications to program code. In this paper, we propose GCAPS, a GPU Context-Aware Preemptive Scheduling approach for real-time GPU tasks. Our approach exerts control over GPU context scheduling at the device driver level and enables preemption of GPU execution based on task priorities by simply adding one-line macros to GPU segment boundaries. In addition, we provide a comprehensive response time analysis of GPU-using tasks for both our proposed approach as well as the default Nvidia GPU driver scheduling that follows a work-conserving round-robin policy. Through empirical evaluations and case studies, we demonstrate the effectiveness of the proposed approaches in improving taskset schedulability and response time. The results highlight significant improvements over prior work as well as the default scheduling approach, with up to 40% higher schedulability, while also achieving predictable worst-case behavior on Nvidia Jetson embedded platforms. 

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3. Near-Optimal Cache Sharing through Co-Located Parallel Scheduling of Threads

   https://doi.org/10.1145/3770858  

   Tessler, Corey; Modekurthy, Venkata Prashant; Fisher, Nathan; Saifullah, Abusayeed; Murphy, Alleyn (January 2026, ACM Transactions on Embedded Computing Systems)

   For hard-real time systems, cache memory increases execution time variability, increasing the complexity of timing analysis. As such, cache memory is often treated exclusively as a detractor to schedulability. Cache-aware co-located scheduling aims at improving schedulability by carefully scheduling threads to share cached values. Cache sharing between threads potentially reduces task execution times and increases schedulability with fewer resources. Antithetically, co-located scheduling may reduce parallelism, decreasing efficiency. Thus, identifying the optimal set of threads to co-locate that minimizes the resources required while ensuring timing constraints is a complex challenge. This work establishes optimal co-location as NP-Hard in the strong sense. It offers an approximation method for the co-located scheduling of Fork-Join tasks named 3-parm-hd. The approximation has a 3-factor guarantee and a resource augmentation bound of 3. The simulated evaluation shows3-parm-hdincreases schedulability compared to an optimal intractable algorithm (without co-location) scheduling 28% more tasks with 30% fewer cores. Simulated results show3-parm-hdoutperforms a 2-factor approximation for traditional makespan, scheduling45% more tasks with41%fewer cores. An experimental RISC-V evaluation running on a QEMU platform confirms the benefits of3-parm-hd, scheduling and executing tasks deemed unschedulable by a 2-factor makespan approximation without co-location. 

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4. CAPA: A Framework for Contention-Aware and Progress-Aware Multi-Core Real-Time Systems

   https://doi.org/10.1109/TC.2026.3688446  

   Chen, Weifan; Izhbirdeev, Ivan; Mancuso, Renato (January 2026, IEEE Transactions on Computers)

   Real-time systems face significant challenges in managing shared resources on multi-core platforms while maintaining temporal predictability. This paper introduces the CAPA (Contention-Aware Progress-Aware) framework for real-time systems to export and leverage runtime progress information to enable informed resource management decisions. CAPA represents a practical model for tracking task progress, extending existing Timely Progress Assessment (TPA) techniques to support complex control flows and concurrent execution on commercial multi-core hardware. Building on this model, it is possible to design progress-aware multi-core schedulers capable of dynamically regulating task execution to meet timing constraints. We implement CAPA on a commercial off-the-shelf (COTS) platform and evaluate its performance. Results demonstrate CAPA’s ability to provide controlled performance degradation, meet timeliness constraints, and improve schedulability. Thus, CAPA represents a significant step forward toward practical, contention-aware scheduling in multi-core real-time systems. 

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5. Latency analysis of self-suspending task chains

   https://doi.org/10.23919/DATE54114.2022.9774655  

   Kloda, Tomasz; Chen, Jiyang; Bertout, Antoine; Sha, Lui; Caccamo, Marco (March 2022, Latency analysis of self-suspending task chains)

   Many cyber-physical systems are offloading computation-heavy programs to hardware accelerators (e.g., GPU and TPU) to reduce execution time. These applications will self-suspend between offloading data to the accelerators and obtaining the returned results. Previous efforts have shown that self-suspending tasks can cause scheduling anomalies, but none has examined inter-task communication. This paper aims to explore self-suspending tasks' data chain latency with periodic activation and asynchronous message passing. We first present the cause for suspension-induced delays and worst-case latency analysis. We then propose a rule for utilizing the hardware co-processors to reduce data chain latency and schedulability analysis. Simulation results show that the proposed strategy can improve overall latency while preserving system schedulability. 

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