Jones, Alexander, and Jha, Rashmi. A Compact Gated-Synapse Model for Neuromorphic Circuits. Retrieved from https://par.nsf.gov/biblio/10291221. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 40.9 Web. doi:10.1109/TCAD.2020.3028534.
Jones, Alexander, & Jha, Rashmi. A Compact Gated-Synapse Model for Neuromorphic Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40 (9). Retrieved from https://par.nsf.gov/biblio/10291221. https://doi.org/10.1109/TCAD.2020.3028534
@article{osti_10291221,
place = {Country unknown/Code not available},
title = {A Compact Gated-Synapse Model for Neuromorphic Circuits},
url = {https://par.nsf.gov/biblio/10291221},
DOI = {10.1109/TCAD.2020.3028534},
abstractNote = {},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
volume = {40},
number = {9},
author = {Jones, Alexander and Jha, Rashmi},
}