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Title: Linearization for High-Speed Current-Steering DACs Using Neural Networks
This paper proposes a novel foreground lineariza- tion scheme for a high-speed current-steering (CS) digital-to- analog converter (DAC). The technique leverages neural networks (NNs) to derive a lookup-table (LUT) that maps the inverse of the DAC transfer characteristic onto the input codes. The algorithm is shown to improve conventional methods by at least 6dB in terms of intermodulation (IM) performance for frequencies up to 9GHz on a state-of-the-art 10-bit CS-DAC operating at 40.96GS/s (gigasamples-per-second) in 14nm CMOS.  more » « less
Award ID(s):
1763747
PAR ID:
10295989
Author(s) / Creator(s):
;
Date Published:
Journal Name:
IEEE 12th Latin America Symposium on Circuits and Systems
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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