More Like this

1. Cache-Out: Leaking Cache Memory Using Hardware Trojan

   https://doi.org/10.1109/TVLSI.2020.2982188  

   Khan, Mohammad Nasim ; De, Asmit ; Ghosh, Swaroop ( June 2020 , IEEE Transactions on Very Large Scale Integration (VLSI) Systems)
2. Kobold: Simplified Cache Coherence for Cache-Attached Accelerators

   https://doi.org/10.1109/LCA.2023.3269399  

   Brana, Jennifer ; Schwedock, Brian C. ; Manerkar, Yatin A. ; Beckmann, Nathan ( January 2023 , IEEE Computer Architecture Letters)
3. Cache automaton

   https://doi.org/10.1145/3123939.3123986  

   Subramaniyan, Arun ; Wang, Jingcheng ; Balasubramanian, Ezhil R. ; Blaauw, David ; Sylvester, Dennis ; Das, Reetuparna ( October 2017 , MICRO-50 '17 Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture)

   Finite State Automata are widely used to accelerate pattern matching in many emerging application domains like DNA sequencing and XML parsing. Conventional CPUs and compute-centric accelerators are bottlenecked by memory bandwidth and irregular memory access patterns in automata processing. We present Cache Automaton, which repurposes last-level cache for automata processing, and a compiler that automates the process of mapping large real world Non-Deterministic Finite Automata (NFAs) to the proposed architecture. Cache Automaton extends a conventional last-level cache architecture with components to accelerate two phases in NFA processing: state-match and state-transition. State-matching is made efficient using a sense-amplifier cycling technique that exploits spatial locality in symbol matches. State-transition is made efficient using a new compact switch architecture. By overlapping these two phases for adjacent symbols we realize an efficient pipelined design. We evaluate two designs, one optimized for performance and the other optimized for space, across a set of 20 diverse benchmarks. The performance optimized design provides a speedup of 15× over DRAM-based Micron's Automata Processor and 3840× speedup over processing in a conventional x86 CPU. The proposed design utilizes on an average 1.2MB of cache space across benchmarks, while consuming 2.3nJ of energy per input symbol. Our space optimized design can reduce the cache utilization to 0.72MB, while still providing a speedup of 9× over AP. 

   more » « less
4. Cache-Aided Interference Management using Hypercube Combinatorial Cache Designs

   https://doi.org/10.1109/ICC.2019.8761238  

   Zhang, Xiang ; Woolsey, Nicholas ; Ji, Mingyue ( May 2019 , ICC 2019 - 2019 IEEE International Conference on Communications (ICC))
5. RL-Cache: Learning-Based Cache Admission for Content Delivery

   https://doi.org/10.1109/JSAC.2020.3000415  

   Kirilin, Vadim ; Sundarrajan, Aditya ; Gorinsky, Sergey ; Sitaraman, Ramesh K. ( June 2020 , IEEE Journal on Selected Areas in Communications)

   Content delivery networks (CDNs) distribute much of the Internet content by caching and serving the objects requested by users. A major goal of a CDN is to maximize the hit rates of its caches, thereby enabling faster content downloads to the users. Content caching involves two components: an admission algorithm to decide whether to cache an object and an eviction algorithm to determine which object to evict from the cache when it is full. In this paper, we focus on cache admission and propose a novel algorithm called RL-Cache that uses model-free reinforcement learning (RL) to decide whether or not to admit a requested object into the CDN’s cache. Unlike prior approaches that use a small set of criteria for decision making, RL-Cache weights a large set of features that include the object size, recency, and frequency of access. We develop a publicly available implementation of RL-Cache and perform an evaluation using production traces for the image, video, and web traffic classes from Akamai’s CDN. The evaluation shows that RL-Cache improves the hit rate in comparison with the state of the art and imposes only a modest resource overhead on the CDN servers. Further, RL-Cache is robust enough that it can be trained in one location and executed on request traces of the same or different traffic classes in other locations of the same geographic region. The paper also reports extensive analyses of the RL-Cache sensitivity to its features and hyperparameter values. The analyses validate the made design choices and reveal interesting insights into the RL-Cache behavior. 

   more » « less