Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress | NSF Public Access Repository

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Citation Details

Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress

Award ID(s):: 1718033

PAR ID:: 10300594

Author(s) / Creator(s):: R. Vazquez, A. Gordon-Ross

Date Published:: 2019-01-01

Journal Name:: International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

Format(s):: Medium: X

Sponsoring Org:: National Science Foundation

Free Publicly Accessible Full Text
Accepted Manuscript1.0
Conference Paper:
https://doi.org/10.1145/3349567.3351730