Abstract To exploit their charge transport properties in transistors, semiconducting carbon nanotubes must be assembled into aligned arrays comprised of individualized nanotubes at optimal packing densities. However, achieving this control on the wafer‐scale is challenging. Here, solution‐based shear in substrate‐wide, confined channels is investigated to deposit continuous films of well‐aligned, individualized, semiconducting nanotubes. Polymer‐wrapped nanotubes in organic ink are forced through sub‐mm tall channels, generating shear up to 10 000 s−1uniformly aligning nanotubes across substrates. The ink volume and concentration, channel height, and shear rate dependencies are elucidated. Optimized conditions enable alignment within a ±32° window, at 50 nanotubes µm−1, on 10 × 10 cm2substrates. Transistors (channel length of 1–5 µm) are fabricated parallel and perpendicular to the alignment. The parallel transistors perform with 7× faster charge carrier mobility (101 and 49 cm2V−1s−1assuming array and parallel‐plate capacitances, respectively) with high on/off ratio of 105. The spatial uniformity varies ±10% in density, ±2° in alignment, and ±7% in mobility. Deposition occurs within seconds per wafer, and further substrate scaling is viable. Compared to random networks, aligned nanotube films promise to be a superior platform for applications including sensors, flexible/stretchable electronics, and light emitting and harvesting devices.
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Dielectrophoresis-Based Positioning of Carbon Nanotubes for Wafer-Scale Fabrication of Carbon Nanotube Devices
In this paper, we report the wafer-scale fabrication of carbon nanotube field-effect transistors (CNTFETs) with the dielectrophoresis (DEP) method. Semiconducting carbon nanotubes (CNTs) were positioned as the active channel material in the fabrication of carbon nanotube field-effect transistors (CNTFETs) with dielectrophoresis (DEP). The drain-source current (IDS) was measured as a function of the drain-source voltage (VDS) and gate-source voltage (VGS) from each CNTFET on the fabricated wafer. The IDS on/off ratio was derived for each CNTFET. It was found that 87% of the fabricated CNTFETs was functional, and that among the functional CNTFETs, 30% of the CNTFETs had an IDS on/off ratio larger than 20 while 70% of the CNTFETs had an IDS on/off ratio lower than 20. The highest IDS on/off ratio was about 490. The DEP-based positioning of carbon nanotubes is simple and effective, and the DEP-based device fabrication steps are compatible with Si technology processes and could lead to the wafer-scale fabrication of CNT electronic devices.
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- Award ID(s):
- 1740687
- PAR ID:
- 10303184
- Date Published:
- Journal Name:
- Micromachines
- Volume:
- 12
- Issue:
- 1
- ISSN:
- 2072-666X
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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