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1. Large Enhancement of Critical Current in Superconducting Devices by Gate Voltage

   Mirko Rocci, Dhavala Suri (December 2020, Nano letters)

   null (Ed.)

   Significant control over the properties of a high-carrier density superconductor via an applied electric field has been considered infeasible due to screening of the field over atomic length scales. Here, we demonstrate an enhancement of up to 30% in critical current in a back-gate tunable NbN micro- and nano superconducting bridges. Our suggested plausible mechanism of this enhancement in critical current based on surface nucleation and pinning of Abrikosov vortices is consistent with expectations and observations for type-II superconductor films with thicknesses comparable to their coherence length. Furthermore, we demonstrate an applied electric field-dependent infinite electroresistance and hysteretic resistance. Our work presents an electric field driven enhancement in the superconducting property in type-II superconductors which is a crucial step toward the understanding of field-effects on the fundamental properties of a superconductor and its exploitation for logic and memory applications in a superconductor-based low-dissipation digital computing paradigm. 

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2. An Active Gate Driver Control Scheme for Steady-State Current Balancing of Paralleled SiC MOSFETs

   https://doi.org/10.1109/TCSII.2024.3378710  

   Lin, Nan; Hmoud, Ahmad_Jaber_Radi Al; Zhao, Yue (January 2024, IEEE Transactions on Circuits and Systems II: Express Briefs)
3. GaN/AlN Schottky-gate p-channel HFETs with InGaN contacts and 100 mA/mm on-current

   https://doi.org/10.1109/IEDM19573.2019.8993532  

   Bader, S. J.; Chaudhuri, R.; Hickman, A.; Nomoto, K.; Bharadwaj, S.; Then, H. W.; Xing, H. G.; Jena, D. (December 2019, IEDM Proceedings 2019)
4. Tuning Gate Potential Profiles and Current–Voltage Characteristics of Polymer Electrolyte-Gated Transistors by Capacitance Engineering

   https://doi.org/10.1021/acsami.4c00079  

   Cho, Kyung Gook; Lee, Keun Hyung; Frisbie, C. Daniel (April 2024, ACS Applied Materials & Interfaces)

   We demonstrate that the transfer characteristics of electrolyte-gated transistors (EGTs) with polythiophene semiconductor channels are a strong function of gate/electrolyte interfacial contact area, i.e., gate size. Polythiophene EGTs with gate/electrolyte areas much larger than the channel/electrolyte areas show a clear peak in the drain current vs gate voltage (ID–VG) behavior, as well as peak voltage hysteresis between the forward and reverse VG sweeps. Polythiophene EGTs with small gate/electrolyte areas, on the other hand, exhibit current plateaus in the ID–VG behavior and a gate-size-dependent hysteresis loop between turn on and off. The qualitatively different transport behaviors are attributed to the relative sizes of the gate/electrolyte and channel/electrolyte interface capacitances, which are proportional to interfacial area. These interfacial capacitances are in series with each other such that the total capacitance of the full gate/electrolyte/channel stack is dominated by the interface with the smallest capacitance or area. For EGTs with large gates, most of the applied VG is dropped at the channel/electrolyte interface, leading to very high charge accumulations, up to ∼0.3 holes per ring (hpr) in the case of polythiophene semiconductors. The large charge density results in sub-band-filling and a marked decrease in hole mobility, giving rise to the peak in ID–VG. For EGTs with small gates, hole accumulation saturates near 0.15 hpr, band-filling does not occur, and hole mobility is maintained at a fixed value, which leads to the ID plateau. Potential drops at the interfaces are confirmed by in situ potential measurements inside a gate/electrolyte/polymer semiconductor stack. Hole accumulations are measured with gate current-gate voltage (IG–VG) measurements acquired simultaneously with the ID–VG characteristics. Overall, our measurements demonstrate that remarkably different ID behavior can be obtained for polythiophene EGTs by controlling the magnitude of the gate-electrolyte interfacial capacitance. 

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5. GaN/AIN Schottky-gate p-channel HFETs with InGaN contacts and 100 mA/mm on-current

   Bader, S.J (January 2019, IED)

   High-performance wide-bandgap p-channel devices which can be monolithically integrated with established wide-bandgap n-channel devices are broadly desirable to expand the design topologies available in power/RF electronics. This work advances the GaN-on-AIN platform as the most promising p-channel contender to enable wide-bandgap complementary electronics. Toward that end, a new generation of GaN-on-AIN-p-channel HFETs is fabricated with on-current exceeding 100mA/mm at room temperature under moderate drain bias. Key fabrication ingredients to this success are discussed, low-temperature characterizations is shared, and new results are benchmarked against the broader literature. 

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