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  • A Resolution-Adaptive 8 mm 2 9.98 Gb/s 39.7 pJ/b 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS
Title: A Resolution-Adaptive 8 mm 2 9.98 Gb/s 39.7 pJ/b 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS
All-digital millimeter-wave (mmWave) massive multi-user multiple-input multiple-output (MU-MIMO) receivers enable extreme data rates but require high power consumption. In order to reduce power consumption, this paper presents the first resolution-adaptive all-digital receiver ASIC that is able to adjust the resolution of the data-converters and baseband-processing engine to the instantaneous communication scenario. The scalable 32-antenna, 65 nm CMOS receiver occupies a total area of 8 mm 2 and integrates analog-to-digital converters (ADCs) with programmable gain and resolution, beamspace channel estimation, and a resolution-adaptive processing-in-memory spatial equalizer. With 6-bit ADC samples and a 4-bit spatial equalizer, our ASIC achieves a throughput of 9.98 Gb/s while being at least 2× more energy-efficient than state-of-the-art designs.  more » « less
Award ID(s):
1717559
PAR ID:
10315883
Author(s) / Creator(s):
; ; ; ; ; ;
Date Published:
Journal Name:
IEEE 47th European Solid State Circuits Conference (ESSCIRC)
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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