Chiu, Po-Wei, and Kim, Chris H. A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors. Retrieved from https://par.nsf.gov/biblio/10325009. IEEE Transactions on Circuits and Systems I: Regular Papers 69.5 Web. doi:10.1109/TCSI.2022.3143876.

Chiu, Po-Wei, & Kim, Chris H. A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors. IEEE Transactions on Circuits and Systems I: Regular Papers, 69 (5). Retrieved from https://par.nsf.gov/biblio/10325009. https://doi.org/10.1109/TCSI.2022.3143876

Chiu, Po-Wei, and Kim, Chris H. "A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors". IEEE Transactions on Circuits and Systems I: Regular Papers 69 (5). Country unknown/Code not available. https://doi.org/10.1109/TCSI.2022.3143876. https://par.nsf.gov/biblio/10325009.

@article{osti_10325009,
place = {Country unknown/Code not available}, title = {A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors}, url = {https://par.nsf.gov/biblio/10325009}, DOI = {10.1109/TCSI.2022.3143876}, abstractNote = {}, journal = {IEEE Transactions on Circuits and Systems I: Regular Papers}, volume = {69}, number = {5}, author = {Chiu, Po-Wei and Kim, Chris H.}, }