Pu, Haoran, Malekzadeh-Arasteh, Omid, Danesh, Ahmad Reza, Nenadic, Zoran, Do, An H., and Heydari, Payam. A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression. Retrieved from https://par.nsf.gov/biblio/10325083. IEEE Journal of Solid-State Circuits . Web. doi:10.1109/JSSC.2021.3108578.

Pu, Haoran, Malekzadeh-Arasteh, Omid, Danesh, Ahmad Reza, Nenadic, Zoran, Do, An H., & Heydari, Payam. A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression. IEEE Journal of Solid-State Circuits, (). Retrieved from https://par.nsf.gov/biblio/10325083. https://doi.org/10.1109/JSSC.2021.3108578

Pu, Haoran, Malekzadeh-Arasteh, Omid, Danesh, Ahmad Reza, Nenadic, Zoran, Do, An H., and Heydari, Payam. "A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression". IEEE Journal of Solid-State Circuits (). Country unknown/Code not available. https://doi.org/10.1109/JSSC.2021.3108578. https://par.nsf.gov/biblio/10325083.

@article{osti_10325083,
place = {Country unknown/Code not available}, title = {A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression}, url = {https://par.nsf.gov/biblio/10325083}, DOI = {10.1109/JSSC.2021.3108578}, abstractNote = {}, journal = {IEEE Journal of Solid-State Circuits}, author = {Pu, Haoran and Malekzadeh-Arasteh, Omid and Danesh, Ahmad Reza and Nenadic, Zoran and Do, An H. and Heydari, Payam}, }